diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-05-15 11:04:39 -0600 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-28 03:12:12 +0000 |
| commit | e3f564988b7d893bfe681f3f93bb2a89d36f9b01 (patch) | |
| tree | eadf043a7f7df7ace25cf296642d4820237c66d9 /src/mainboard/google/dedede/variants/waddledoo/Makefile.inc | |
| parent | b3c41329fdca84a251c183bbc2b0767978e9d96f (diff) | |
mb/google/dedede: Enable Intel Speed Shift Technology
Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in
waddledee and waddledoo variants on early phases.
BUG=b:151281860
TEST=Build and boot the mainboard. Ensure that cpufreq driver to
configure P-states is enabled in kernel on boards where board version is
provisioned.
Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/waddledoo/Makefile.inc')
| -rw-r--r-- | src/mainboard/google/dedede/variants/waddledoo/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 922c314ee3..11bbbd60cc 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -4,3 +4,5 @@ SPD_SOURCES = empty #0b0000 SPD_SOURCES += SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0001 romstage-y += memory.c + +ramstage-y += variant.c |