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authorTao Xia <xiatao5@huaqin.corp-partner.google.com>2021-01-14 11:19:02 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-19 09:06:03 +0000
commit97fce56b9c9ecb3c5a624d2c55e5ced7cab2d3f5 (patch)
treedb34c253bc3dca2d68b91c150e91374182330c28 /src/mainboard/google/dedede/variants/sasukette/overridetree.cb
parent14d0a6a982d4d53705355ad31d0eeb960d33194c (diff)
mb/google/dedede: Create sasukette variant
Create the sasukette variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:175848514 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKETTE Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I0a554efe0919dc2f5880f0f7817a37bd4be88ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/sasukette/overridetree.cb')
-rw-r--r--src/mainboard/google/dedede/variants/sasukette/overridetree.cb42
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
new file mode 100644
index 0000000000..404024b1d6
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -0,0 +1,42 @@
+chip soc/intel/jasperlake
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Trackpad |
+ #| I2C1 | Digitizer |
+ #| I2C2 | Touchscreen |
+ #| I2C3 | Camera |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ device pci 15.0 on end
+ end
+end