diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2020-05-18 12:17:45 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:30:59 +0000 |
commit | 214c719eed83967b8f0564feca65eebb3d83f5bc (patch) | |
tree | 2d7703ccd8ba66fc7b3d635894b8ea1b6ad4f486 /src/mainboard/google/dedede/dsdt.asl | |
parent | b468d569f6acc2815158ec5ce7d54e20ec98a89b (diff) |
mb/google/dedede: Add mainboard acpi support for GPIO PM configuration
Setting the default values for GPIO community power management, causes
issues in detecting TPM interrupts. So to avoid that GPIO PM has to be
disabled in devicetree. But for S0ix it is needed. This patch implements
a workaround in ASL code to enable GPIO PM on S0ix entry and disable it
on S0ix exit.
This patch adds the following three platform specific methods.
1. MS0X to enable power management features for GPIO communities on
low power mode entry and disables it on exit.
2. MPTS to enable power management features for GPIO communities when
preparing to sleep.
3. MWAK to disable power management features for GPIO communities on
waking up.
BUG=b:153847814
TEST=Verify S0ix is working. GPIO PM configuration is upadated on low
power mode entry and exit.
Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/dsdt.asl')
-rw-r--r-- | src/mainboard/google/dedede/dsdt.asl | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index dce0bf35f0..933ca1a503 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -27,6 +27,9 @@ DefinitionBlock( #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/jasperlake/acpi/southbridge.asl> } + + /* Mainboard hooks */ + #include "acpi/mainboard.asl" } #if CONFIG(VARIANT_HAS_CAMERA_ACPI) @@ -34,6 +37,11 @@ DefinitionBlock( #include <variant/acpi/camera.asl> #endif + + /* Include Low power idle table for a short term workaround to enable + S0ix. Once cr50 pulse width is fixed, this can be removed. */ + #include <soc/intel/common/acpi/lpit.asl> + /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> |