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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-02-07 17:37:17 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 15:36:07 +0000
commit95ea799019fdb7c0baee70bd07196910dbc0cd95 (patch)
treeb8ee169779a55b4e2c55f8e24026c5c74903a80e /src/mainboard/google/dedede/Kconfig
parent2a3cef29d81ab9200b8226be41a09f975c9ed485 (diff)
mb/google/dedede: Add console UART configuration
Enable UART Port 2 as console UART and configure the concerned GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/Kconfig')
-rw-r--r--src/mainboard/google/dedede/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 9b5bd4af5e..c2f66a43eb 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2