diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-02-26 23:03:47 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-03-03 07:41:12 +0000 |
| commit | 872fced41dde0b7d168900a61b916682c5cf7b46 (patch) | |
| tree | 552296f32328201e5f0c4f09089faab9ca965cb0 /src/mainboard/google/dedede/Kconfig | |
| parent | ce622389983f941f5b86907c41c9c843fadccce0 (diff) | |
mb/google/dedede: Add memory initialization support for dedede
Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/Kconfig')
| -rw-r--r-- | src/mainboard/google/dedede/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 3eddabc985..ebca580ffa 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE @@ -31,6 +32,10 @@ config DEVICETREE string default "variants/baseboard/devicetree.cb" +config DIMM_SPD_SIZE + int + default 512 + config DRIVER_TPM_SPI_BUS default 0x1 |