soc/intel/braswell: add default option to use public FSP

The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.

To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.

Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.

Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

8 files changed, 47 insertions, 20 deletions

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index b3c6790e57..aac14c06c3 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN
 	select HAVE_ACPI_RESUME
 	select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN
 	select SYSTEM_TYPE_LAPTOP
+	select USE_GOOGLE_FSP
 
 if BOARD_GOOGLE_BASEBOARD_CYAN
 
diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb
index 2e708af0d6..a1ab510810 100644
--- a/src/mainboard/google/cyan/variants/celes/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb
@@ -73,12 +73,6 @@ chip soc/intel/braswell
 	register "ISPEnable" = "0"		# Disable IUNIT
 	register "ISPPciDevConfig" = "3"
 	register "PcdSdDetectChk" = "0"		# Disable SD card detect
-	# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-	register "D0Usb2Port0PerPortRXISet" = "2"
-	register "D0Usb2Port1PerPortRXISet" = "2"
-	register "D0Usb2Port2PerPortRXISet" = "2"
-	register "D0Usb2Port3PerPortRXISet" = "2"
-	register "D0Usb2Port4PerPortRXISet" = "2"
 
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c
index 88b17f5da7..6c522a1d0c 100644
--- a/src/mainboard/google/cyan/variants/celes/ramstage.c
+++ b/src/mainboard/google/cyan/variants/celes/ramstage.c
@@ -19,29 +19,36 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 {
 	if (SocStepping() >= SocD0) {
 
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
 		params->Usb2Port0PerPortPeTxiSet = 7;
 		params->Usb2Port0PerPortTxiSet = 0;
 		params->Usb2Port0IUsbTxEmphasisEn = 3;
 		params->Usb2Port0PerPortTxPeHalf = 1;
+		params->D0Usb2Port0PerPortRXISet = 2;
 
 		params->Usb2Port1PerPortPeTxiSet = 7;
 		params->Usb2Port1PerPortTxiSet = 0;
 		params->Usb2Port1IUsbTxEmphasisEn = 3;
 		params->Usb2Port1PerPortTxPeHalf = 1;
+		params->D0Usb2Port1PerPortRXISet = 2;
 
 		params->Usb2Port2PerPortPeTxiSet = 7;
 		params->Usb2Port2PerPortTxiSet = 6;
 		params->Usb2Port2IUsbTxEmphasisEn = 3;
 		params->Usb2Port2PerPortTxPeHalf = 1;
+		params->D0Usb2Port2PerPortRXISet = 2;
 
 		params->Usb2Port3PerPortPeTxiSet = 7;
 		params->Usb2Port3PerPortTxiSet = 6;
 		params->Usb2Port3IUsbTxEmphasisEn = 3;
 		params->Usb2Port3PerPortTxPeHalf = 1;
+		params->D0Usb2Port3PerPortRXISet = 2;
 
 		params->Usb2Port4PerPortPeTxiSet = 7;
 		params->Usb2Port4PerPortTxiSet = 6;
 		params->Usb2Port4IUsbTxEmphasisEn = 3;
 		params->Usb2Port4PerPortTxPeHalf = 1;
+		params->D0Usb2Port4PerPortRXISet = 2;
 	}
 }
diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc
index 5e94e715fa..7799e8d2b3 100644
--- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc
+++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc
@@ -18,6 +18,7 @@ romstage-y += romstage.c
 romstage-y += spd_util.c
 
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
 
 SPD_BIN = $(obj)/spd.bin
 
diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb
index 1ce056f32e..807dbcb2fe 100644
--- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/kefka/devicetree.cb
@@ -80,13 +80,6 @@ chip soc/intel/braswell
 	register "I2C5Frequency" = "1"
 	register "I2C6Frequency" = "1"
 
-        # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-        register "D0Usb2Port0PerPortRXISet" = "2"
-        register "D0Usb2Port1PerPortRXISet" = "2"
-        register "D0Usb2Port2PerPortRXISet" = "2"
-        register "D0Usb2Port3PerPortRXISet" = "2"
-        register "D0Usb2Port4PerPortRXISet" = "2"
-
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c
new file mode 100644
index 0000000000..d790708cce
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+
+void board_silicon_USB2_override(SILICON_INIT_UPD *params)
+{
+	if (SocStepping() >= SocD0) {
+
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
+		params->D0Usb2Port0PerPortRXISet = 2;
+		params->D0Usb2Port1PerPortRXISet = 2;
+		params->D0Usb2Port2PerPortRXISet = 2;
+		params->D0Usb2Port3PerPortRXISet = 2;
+		params->D0Usb2Port4PerPortRXISet = 2;
+	}
+}
diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb
index 65e662c5dd..e1bbb0ac5b 100644
--- a/src/mainboard/google/cyan/variants/relm/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb
@@ -80,13 +80,6 @@ chip soc/intel/braswell
 	register "I2C5Frequency" = "1"
 	register "I2C6Frequency" = "1"
 
-	# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-	register "D0Usb2Port0PerPortRXISet" = "2"
-	register "D0Usb2Port1PerPortRXISet" = "2"
-	register "D0Usb2Port2PerPortRXISet" = "2"
-	register "D0Usb2Port3PerPortRXISet" = "2"
-	register "D0Usb2Port4PerPortRXISet" = "2"
-
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c
index 27f9dfa241..3fbd2aebd9 100644
--- a/src/mainboard/google/cyan/variants/relm/ramstage.c
+++ b/src/mainboard/google/cyan/variants/relm/ramstage.c
@@ -36,5 +36,13 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 		params->Usb2Port3PerPortTxiSet = 0;
 		params->Usb2Port3IUsbTxEmphasisEn = 2;
 		params->Usb2Port3PerPortTxPeHalf = 1;
+
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
+		params->D0Usb2Port0PerPortRXISet = 2;
+		params->D0Usb2Port1PerPortRXISet = 2;
+		params->D0Usb2Port2PerPortRXISet = 2;
+		params->D0Usb2Port3PerPortRXISet = 2;
+		params->D0Usb2Port4PerPortRXISet = 2;
 	}
 }