mb/google/cyan: convert to overridetree

Simply cyan variants by converting to overridetree format.

A few differences were ignored as there appears to be no
reason behind them:

- cyan had PCIe RP2 enabled, but nothing is attached to it
- kefka had the SPI 1 device disabled
- reks, relm, and ultima had HSUART 1 disabled
- edgar had I2C1 UPD disabled

Test: build/boot cyan and edgar variants, verify everything
still works

Change-Id: I9928cc59adcfda4661ddfdfa95f53a7820053b4a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

23 files changed, 216 insertions, 1455 deletions

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index 45610542e4..92bafee514 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -68,9 +68,9 @@ config MAINBOARD_PART_NUMBER
 	default "Ultima" if BOARD_GOOGLE_ULTIMA
 	default "Wizpig" if BOARD_GOOGLE_WIZPIG
 
-config DEVICETREE
+config OVERRIDE_DEVICETREE
 	string
-	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config CBFS_SIZE
 	hex
diff --git a/src/mainboard/google/cyan/variants/terra/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index d7d0f1f7e8..328a60817e 100644
--- a/src/mainboard/google/cyan/variants/terra/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -27,12 +27,12 @@ chip soc/intel/braswell
 	register "PcdEnableLpe" = "1"
 	register "PcdEnableDma0" = "1"
 	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "0"
-	register "PcdEnableI2C1" = "1"
+	register "PcdEnableI2C0" = "0"		# Touchscreen
+	register "PcdEnableI2C1" = "1"		# PMIC (or Maxim Audio)
 	register "PcdEnableI2C2" = "0"
 	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
+	register "PcdEnableI2C4" = "1"		# Realtek Audio
+	register "PcdEnableI2C5" = "1"		# Touchpad
 	register "PcdEnableI2C6" = "0"
 	register "PunitPwrConfigDisable" = "0"	# Enable SVID
 	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
@@ -67,13 +67,14 @@ chip soc/intel/braswell
 	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
 	register "PcdSataInterfaceSpeed" = "3"
 	register "PcdPchSsicEnable" = "1"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
+	register "PcdRtcLock" = "0"		# Disable RTC access locking to NVRAM
 	register "PMIC_I2CBus" = "1"
 	register "ISPEnable" = "0"		# Disable IUNIT
 	register "ISPPciDevConfig" = "3"
 	register "PcdSdDetectChk" = "0"		# Disable SD card detect
+
 	register "I2C0Frequency" = "1"
-	register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
+	register "I2C1Frequency" = "2"		# Set the PMIC clock speed to 1Mhz
 	register "I2C2Frequency" = "1"
 	register "I2C3Frequency" = "1"
 	register "I2C4Frequency" = "1"
@@ -100,37 +101,37 @@ chip soc/intel/braswell
 	end
 	device domain 0 on
 					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
+		device pci 00.0 on  end	# 8086 2280 - SoC transaction router
+		device pci 02.0 on  end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
 		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
+		device pci 0b.0 on  end	# 8086 22dc - Signal Processing Controller
+		device pci 10.0 on  end	# 8086 2294 - MMC Port
 		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
+		device pci 12.0 on  end	# 8086 0F16 - SD Port
 		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
+		device pci 14.0 on  end	# 8086 22b5 - USB XHCI
+		device pci 15.0 on  end	# 8086 22a8 - LP Engine Audio
 		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
+		device pci 18.0 on  end	# 8086 22c0 - SIO - DMA
+		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1: Touchscreen
+		device pci 18.2 on  end	# 8086 22c2 -   I2C Port 2: PMIC
 		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
 		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
+		device pci 18.5 on  end	# 8086 22c5 -   I2C Port 5: Realtek Audio
+		device pci 18.6 on  end	# 8086 22c6 -   I2C Port 6: Touchpad
 		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
 		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
+		device pci 1b.0 on  end	# 8086 2284 - HD Audio
+		device pci 1c.0 on  end	# 8086 22c8 - PCIe Root Port 1
+		device pci 1c.1 off end	# 8086 22ca - PCIe Root Port 2
+		device pci 1c.2 on  end	# 8086 22cc - PCIe Root Port 3: WiFi
+		device pci 1c.3 off end	# 8086 22ce - PCIe Root Port 4
+		device pci 1e.0 on  end	# 8086 2286 - SIO - DMA
 		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
 		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
+		device pci 1e.3 on  end	# 8086 228a -   HSUART 1
 		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
+		device pci 1e.5 on  end	# 8086 228e -   SPI 1
 		device pci 1e.6 off end	# 8086 2290 -   SPI 2
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
diff --git a/src/mainboard/google/cyan/variants/banon/devicetree.cb b/src/mainboard/google/cyan/variants/banon/devicetree.cb
deleted file mode 100644
index 60076c2171..0000000000
--- a/src/mainboard/google/cyan/variants/banon/devicetree.cb
+++ /dev/null
@@ -1,146 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "0"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "6"
-	register "Usb2Port0IUsbTxEmphasisEn" = "3"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "6"
-	register "Usb2Port1IUsbTxEmphasisEn" = "3"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "6"
-	register "Usb2Port2IUsbTxEmphasisEn" = "3"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "6"
-	register "Usb2Port3IUsbTxEmphasisEn" = "3"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "6"
-	register "Usb2Port4IUsbTxEmphasisEn" = "3"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "1"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-	register "I2C0Frequency" = "1"
-	register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
-	register "I2C2Frequency" = "1"
-	register "I2C3Frequency" = "1"
-	register "I2C4Frequency" = "1"
-	register "I2C5Frequency" = "1"
-	register "I2C6Frequency" = "1"
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/banon/overridetree.cb b/src/mainboard/google/cyan/variants/banon/overridetree.cb
new file mode 100644
index 0000000000..32f0dc6a5f
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/banon/overridetree.cb
@@ -0,0 +1,26 @@
+chip soc/intel/braswell
+
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "6"
+	register "Usb2Port0IUsbTxEmphasisEn" = "3"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "6"
+	register "Usb2Port1IUsbTxEmphasisEn" = "3"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "6"
+	register "Usb2Port2IUsbTxEmphasisEn" = "3"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "6"
+	register "Usb2Port3IUsbTxEmphasisEn" = "3"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "6"
+	register "Usb2Port4IUsbTxEmphasisEn" = "3"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+
+	device domain 0 on end
+
+end
diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb
deleted file mode 100644
index a1ab510810..0000000000
--- a/src/mainboard/google/cyan/variants/celes/devicetree.cb
+++ /dev/null
@@ -1,140 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "0"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "0"
-	register "PcdPchUsbHsicPort" = "0"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0"		# Disable SD card detect
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/celes/overridetree.cb b/src/mainboard/google/cyan/variants/celes/overridetree.cb
new file mode 100644
index 0000000000..1eabd8e315
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/celes/overridetree.cb
@@ -0,0 +1,8 @@
+chip soc/intel/braswell
+
+	register "PcdPchSsicEnable" = "0"
+	register "PcdPchUsbHsicPort" = "0"
+
+	device domain 0 on end
+
+end
diff --git a/src/mainboard/google/cyan/variants/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb
deleted file mode 100644
index dd9b05e5f7..0000000000
--- a/src/mainboard/google/cyan/variants/cyan/devicetree.cb
+++ /dev/null
@@ -1,139 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "0"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "0"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_CONFIG1"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "1"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "0"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 off end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 2284 - HD Audio
-		device pci 1c.0 on end	# 8086 22c8 - PCIe Root Port 1
-		device pci 1c.1 on end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 22cc - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/cyan/overridetree.cb b/src/mainboard/google/cyan/variants/cyan/overridetree.cb
new file mode 100644
index 0000000000..10df7ab023
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/cyan/overridetree.cb
@@ -0,0 +1,18 @@
+chip soc/intel/braswell
+
+	register "PcdCaMirrorEn" = "0"
+
+	register "PcdEnableI2C0" = "1"	# Touchscreen
+	register "PcdEnableI2C4" = "0"	# No Realtek Audio
+
+	register "ChvSvidConfig" = "SVID_CONFIG1"
+
+	register "PMIC_I2CBus" = "0"
+
+	register "I2C1Frequency" = "1"
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+		device pci 18.5 off end	# 8086 22c5 - I2C Port 5: Realtek Audio
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/edgar/devicetree.cb b/src/mainboard/google/cyan/variants/edgar/devicetree.cb
deleted file mode 100644
index 0ba221e3a6..0000000000
--- a/src/mainboard/google/cyan/variants/edgar/devicetree.cb
+++ /dev/null
@@ -1,140 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_DISABLED"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "0"
-	register "PcdEnableI2C1" = "0"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "6"
-	register "Usb2Port3IUsbTxEmphasisEn" = "3"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "0"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "0"
-	register "PcdPchUsbHsicPort" = "0"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 off end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/edgar/overridetree.cb b/src/mainboard/google/cyan/variants/edgar/overridetree.cb
new file mode 100644
index 0000000000..48b10134f7
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/edgar/overridetree.cb
@@ -0,0 +1,32 @@
+chip soc/intel/braswell
+
+	register "PcdSdcardMode" = "PCH_DISABLED"
+
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "5"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "3"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "3"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "6"
+	register "Usb2Port3IUsbTxEmphasisEn" = "3"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "0"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+
+	register "PcdPchSsicEnable" = "0"
+	register "PcdPchUsbHsicPort" = "0"
+
+	device domain 0 on
+		device pci 12.0 off end	# 8086 0F16 - SD Port
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb
deleted file mode 100644
index 807dbcb2fe..0000000000
--- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb
+++ /dev/null
@@ -1,146 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "1"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-	register "I2C0Frequency" = "1"
-	register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
-	register "I2C2Frequency" = "1"
-	register "I2C3Frequency" = "1"
-	register "I2C4Frequency" = "1"
-	register "I2C5Frequency" = "1"
-	register "I2C6Frequency" = "1"
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 off end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/kefka/overridetree.cb b/src/mainboard/google/cyan/variants/kefka/overridetree.cb
new file mode 100644
index 0000000000..41908e0d4c
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/kefka/overridetree.cb
@@ -0,0 +1,8 @@
+chip soc/intel/braswell
+
+	register "PcdEnableI2C0" = "1"		# Touchscreen
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/reks/devicetree.cb b/src/mainboard/google/cyan/variants/reks/devicetree.cb
deleted file mode 100644
index 302f2da620..0000000000
--- a/src/mainboard/google/cyan/variants/reks/devicetree.cb
+++ /dev/null
@@ -1,137 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "7"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "1"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0"		# Disable SD card detect
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 off end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/reks/overridetree.cb b/src/mainboard/google/cyan/variants/reks/overridetree.cb
new file mode 100644
index 0000000000..9b10656b2e
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/reks/overridetree.cb
@@ -0,0 +1,29 @@
+chip soc/intel/braswell
+
+	register "PcdEnableI2C0" = "1"		# Touchscreen
+
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "5"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "7"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "3"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "3"
+	register "Usb2Port3IUsbTxEmphasisEn" = "2"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "3"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb
deleted file mode 100644
index e1bbb0ac5b..0000000000
--- a/src/mainboard/google/cyan/variants/relm/devicetree.cb
+++ /dev/null
@@ -1,146 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "1"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-	register "I2C0Frequency" = "1"
-	register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
-	register "I2C2Frequency" = "1"
-	register "I2C3Frequency" = "1"
-	register "I2C4Frequency" = "1"
-	register "I2C5Frequency" = "1"
-	register "I2C6Frequency" = "1"
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 off end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/relm/overridetree.cb b/src/mainboard/google/cyan/variants/relm/overridetree.cb
new file mode 100644
index 0000000000..41908e0d4c
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/relm/overridetree.cb
@@ -0,0 +1,8 @@
+chip soc/intel/braswell
+
+	register "PcdEnableI2C0" = "1"		# Touchscreen
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/setzer/devicetree.cb b/src/mainboard/google/cyan/variants/setzer/devicetree.cb
deleted file mode 100644
index f0b2c6f976..0000000000
--- a/src/mainboard/google/cyan/variants/setzer/devicetree.cb
+++ /dev/null
@@ -1,146 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "0"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-	register "I2C0Frequency" = "1"
-	register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
-	register "I2C2Frequency" = "1"
-	register "I2C3Frequency" = "1"
-	register "I2C4Frequency" = "1"
-	register "I2C5Frequency" = "1"
-	register "I2C6Frequency" = "1"
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/setzer/overridetree.cb b/src/mainboard/google/cyan/variants/setzer/overridetree.cb
new file mode 100644
index 0000000000..d3d7f8dbc7
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/setzer/overridetree.cb
@@ -0,0 +1,10 @@
+chip soc/intel/braswell
+
+	register "PcdEnableI2C0" = "1"		# Touchscreen
+
+	register "PcdPchSsicEnable" = "0"
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/terra/overridetree.cb b/src/mainboard/google/cyan/variants/terra/overridetree.cb
new file mode 100644
index 0000000000..8b6b0078cd
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/terra/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/braswell
+
+	device domain 0 on end
+
+end
diff --git a/src/mainboard/google/cyan/variants/ultima/devicetree.cb b/src/mainboard/google/cyan/variants/ultima/devicetree.cb
deleted file mode 100644
index d4ed38b430..0000000000
--- a/src/mainboard/google/cyan/variants/ultima/devicetree.cb
+++ /dev/null
@@ -1,140 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "0"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "5"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "3"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "3"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "3"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "0"
-	register "PcdPchUsbHsicPort" = "0"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0"		# Disable SD card detect
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 2284 - HD Audio
-		device pci 1c.0 on end	# 8086 22c8 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 22cc - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 off end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/ultima/overridetree.cb b/src/mainboard/google/cyan/variants/ultima/overridetree.cb
new file mode 100644
index 0000000000..b5aa652292
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/ultima/overridetree.cb
@@ -0,0 +1,11 @@
+chip soc/intel/braswell
+
+	register "PcdEnableI2C0" = "1"		# Touchscreen
+
+	register "PcdPchSsicEnable" = "0"
+	register "PcdPchUsbHsicPort" = "0"
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+	end
+end
diff --git a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb b/src/mainboard/google/cyan/variants/wizpig/devicetree.cb
deleted file mode 100644
index 7be7a0f792..0000000000
--- a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb
+++ /dev/null
@@ -1,147 +0,0 @@
-chip soc/intel/braswell
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
-
-	register "PcdMrcInitMmioSize" = "0x0800"
-	register "PcdMrcInitSpdAddr1" = "0xa0"
-	register "PcdMrcInitSpdAddr2" = "0xa2"
-	register "PcdIgdDvmt50PreAlloc" = "1"
-	register "PcdApertureSize" = "2"
-	register "PcdGttSize" = "1"
-	register "PcdDvfsEnable" = "1"
-	register "PcdCaMirrorEn" = "1"
-
-	############################################################
-	# Set the parameters for SiliconInit
-	############################################################
-
-	register "PcdSdcardMode" = "PCH_ACPI_MODE"
-	register "PcdEnableHsuart0" = "0"
-	register "PcdEnableHsuart1" = "1"
-	register "PcdEnableAzalia" = "1"
-	register "PcdEnableXhci" = "1"
-	register "PcdEnableLpe" = "1"
-	register "PcdEnableDma0" = "1"
-	register "PcdEnableDma1" = "1"
-	register "PcdEnableI2C0" = "1"
-	register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "0"
-	register "PcdEnableI2C3" = "0"
-	register "PcdEnableI2C4" = "1"
-	register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "0"
-	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
-	register "PcdEmmcMode" = "PCH_ACPI_MODE"
-	register "PcdUsb3ClkSsc" = "1"
-	register "PcdDispClkSsc" = "1"
-	register "PcdSataClkSsc" = "1"
-	register "PcdEnableSata" = "0"		# Disable SATA
-	register "Usb2Port0PerPortPeTxiSet" = "7"
-	register "Usb2Port0PerPortTxiSet" = "0"
-	register "Usb2Port0IUsbTxEmphasisEn" = "2"
-	register "Usb2Port0PerPortTxPeHalf" = "1"
-	register "Usb2Port1PerPortPeTxiSet" = "7"
-	register "Usb2Port1PerPortTxiSet" = "0"
-	register "Usb2Port1IUsbTxEmphasisEn" = "2"
-	register "Usb2Port1PerPortTxPeHalf" = "1"
-	register "Usb2Port2PerPortPeTxiSet" = "7"
-	register "Usb2Port2PerPortTxiSet" = "0"
-	register "Usb2Port2IUsbTxEmphasisEn" = "2"
-	register "Usb2Port2PerPortTxPeHalf" = "1"
-	register "Usb2Port3PerPortPeTxiSet" = "7"
-	register "Usb2Port3PerPortTxiSet" = "0"
-	register "Usb2Port3IUsbTxEmphasisEn" = "2"
-	register "Usb2Port3PerPortTxPeHalf" = "1"
-	register "Usb2Port4PerPortPeTxiSet" = "7"
-	register "Usb2Port4PerPortTxiSet" = "3"
-	register "Usb2Port4IUsbTxEmphasisEn" = "2"
-	register "Usb2Port4PerPortTxPeHalf" = "1"
-	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
-	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
-	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
-	register "PcdSataInterfaceSpeed" = "3"
-	register "PcdPchSsicEnable" = "0"
-	register "PcdPchUsbHsicPort" = "0"
-	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
-	register "PMIC_I2CBus" = "1"
-	register "ISPEnable" = "0"		# Disable IUNIT
-	register "ISPPciDevConfig" = "3"
-	register "PcdSdDetectChk" = "0" # Disable SD card detect
-	register "I2C0Frequency" = "1"
-	register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
-	register "I2C2Frequency" = "1"
-	register "I2C3Frequency" = "1"
-	register "I2C4Frequency" = "1"
-	register "I2C5Frequency" = "1"
-	register "I2C6Frequency" = "1"
-
-	# LPE audio codec settings
-	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
-
-	# Enable devices in ACPI mode
-	register "lpss_acpi_mode" = "1"
-	register "emmc_acpi_mode" = "1"
-	register "sd_acpi_mode" = "1"
-	register "lpe_acpi_mode" = "1"
-
-	# Disable SLP_X stretching after SUS power well fail.
-	register "disable_slp_x_stretch_sus_fail" = "1"
-
-	# Allow PCIe devices to wake system from suspend
-	register "pcie_wake_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-					# EDS Table 24-4, Figure 24-5
-		device pci 00.0 on end	# 8086 2280 - SoC transaction router
-		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
-		device pci 0b.0 on end	# 8086 22dc - ?
-		device pci 10.0 on end	# 8086 2294 - MMC Port
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port
-		device pci 12.0 on end	# 8086 0F16 - SD Port
-		device pci 13.0 off end	# 8086 22a3 - Sata controller
-		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
-		device pci 16.0 off end	# 8086 22b7 - USB device
-		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
-		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
-		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
-		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
-		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 on end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
-		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
-		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
-		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 off end	# 8086 228c -   HSUART 2
-		device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 off end	# 8086 2290 -   SPI 2
-		device pci 1e.7 off end	# 8086 22ac -   SPI 3
-		device pci 1f.0 on	# 8086 229c - LPC bridge
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Bridge
-		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/google/cyan/variants/wizpig/overridetree.cb b/src/mainboard/google/cyan/variants/wizpig/overridetree.cb
new file mode 100644
index 0000000000..5923462147
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/wizpig/overridetree.cb
@@ -0,0 +1,32 @@
+chip soc/intel/braswell
+
+	register "PcdEnableI2C0" = "1"		# Touchscreen
+
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "0"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "0"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "0"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "0"
+	register "Usb2Port3IUsbTxEmphasisEn" = "2"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "3"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+
+	register "PcdPchSsicEnable" = "0"
+	register "PcdPchUsbHsicPort" = "0"
+
+	device domain 0 on
+		device pci 18.1 on  end	# 8086 22c1 - I2C Port 1: Touchscreen
+	end
+end