google/cyan: fix variant memory/silicon init params override

The mainboard_memory_init_params() and mainboard_silicon_init_params()
methods already have weak definitions in drivers/intel/fsp1_1,
so having them declared as weak in the cyan baseboard has the effect
of them not being called at all unless overridden at the variant level.

Therefore, remove the weak declarations in the baseboard and ensure
that each variant has its own init functions if needed.

TEST: build/boot google/cyan

Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

7 files changed, 31 insertions, 33 deletions

diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc
index 0b11aa3b1d..92b0422279 100644
--- a/src/mainboard/google/cyan/Makefile.inc
+++ b/src/mainboard/google/cyan/Makefile.inc
@@ -21,10 +21,10 @@ romstage-y += spd/spd.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-y += irqroute.c
-ramstage-y += ramstage.c
 ramstage-y += w25q64.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
index 57c40e09bd..c164ea4792 100644
--- a/src/mainboard/google/cyan/romstage.c
+++ b/src/mainboard/google/cyan/romstage.c
@@ -15,6 +15,7 @@
  */
 
 #include <soc/romstage.h>
+#include <baseboard/variants.h>
 #include <chip.h>
 
 /* All FSP specific code goes in this block */
@@ -28,15 +29,23 @@ void mainboard_romstage_entry(struct romstage_params *rp)
 	romstage_common(rp);
 }
 
-__attribute__ ((weak))
 void mainboard_memory_init_params(struct romstage_params *params,
 	MEMORY_INIT_UPD *memory_params)
 {
 	/* Update SPD data */
-	if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN))
+		memory_params->PcdMemoryTypeEnable = MEM_DDR3;
+	else
 		memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
-	}
 	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
 	memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
 	memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
+
+	/* Variant-specific memory params */
+	variant_memory_init_params(memory_params);
+}
+
+__attribute__ ((weak))
+void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
+{
 }
diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c
index dab80b0cef..e516bb8446 100644
--- a/src/mainboard/google/cyan/variants/banon/romstage.c
+++ b/src/mainboard/google/cyan/variants/banon/romstage.c
@@ -15,11 +15,10 @@
  */
 
 #include <soc/romstage.h>
-#include <chip.h>
+#include <baseboard/variants.h>
 #include <mainboard/google/cyan/spd/spd_util.h>
 
-void mainboard_memory_init_params(struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
+void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
 {
 	int ram_id = get_ramid();
 
@@ -45,10 +44,4 @@ void mainboard_memory_init_params(struct romstage_params *params,
 		memory_params->PcdDramDensity = 3;
 		memory_params->PcdDualRankDram = 0;
 	}
-
-	/* Update SPD data */
-	memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
-	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
-	memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
-	memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
 }
diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h
index 093a49bf16..2a16f04d2a 100644
--- a/src/mainboard/google/cyan/ramstage.c
+++ b/src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h
@@ -1,11 +1,12 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2014 Intel Corporation
+ * Copyright (C) 2017 Matt DeVillier
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -13,9 +14,11 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/ramstage.h>
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
 
-__attribute__ ((weak))
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
-{
-}
+#include <soc/romstage.h>
+
+void variant_memory_init_params(MEMORY_INIT_UPD *memory_params);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c
index ac5cd3b0de..88b17f5da7 100644
--- a/src/mainboard/google/cyan/variants/celes/ramstage.c
+++ b/src/mainboard/google/cyan/variants/celes/ramstage.c
@@ -15,7 +15,7 @@
 
 #include <soc/ramstage.h>
 
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 {
 	if (SocStepping() >= SocD0) {
 
diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c
index 6ef4360377..51857f9819 100644
--- a/src/mainboard/google/cyan/variants/terra/ramstage.c
+++ b/src/mainboard/google/cyan/variants/terra/ramstage.c
@@ -17,7 +17,7 @@
 #include <boardid.h>
 #include <variant/onboard.h>
 
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 {
 	uint8_t	boardid = 0;
 	uint8_t	projectid = 0;
diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c
index e670461ff8..8b30d69c92 100644
--- a/src/mainboard/google/cyan/variants/terra/romstage.c
+++ b/src/mainboard/google/cyan/variants/terra/romstage.c
@@ -15,11 +15,10 @@
  */
 
 #include <soc/romstage.h>
-#include <chip.h>
+#include <baseboard/variants.h>
 #include <mainboard/google/cyan/spd/spd_util.h>
 
-void mainboard_memory_init_params(struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
+void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
 {
 	int ram_id = get_ramid();
 
@@ -45,10 +44,4 @@ void mainboard_memory_init_params(struct romstage_params *params,
 		memory_params->PcdDramDensity = 3;
 		memory_params->PcdDualRankDram = 0;
 	}
-
-	/* Update SPD data */
-	memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
-	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
-	memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
-	memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
 }