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author | Matt DeVillier <matt.devillier@gmail.com> | 2017-09-02 20:49:45 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2017-10-15 22:23:05 +0000 |
commit | 94bc265b6437d8793d972efa612579b9c2be0ba3 (patch) | |
tree | 549931de13de926d0943e238ae249acb4f3c8e09 /src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h | |
parent | 81b5bde7e481ab664d581d9c2b17e5b22ac28302 (diff) |
google/ultima: add new board as variant of cyan baseboard
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new ultima variant
Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""
Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h')
-rw-r--r-- | src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h new file mode 100644 index 0000000000..e5b503f4fc --- /dev/null +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/cyan/irqroute.h> + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +#define BOARD_TOUCH_IRQ 184 + +/* DPTF */ +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +/* KBD: Gpio index in N bank */ +#define BOARD_I8042_GPIO_INDEX 17 +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller" +#define AUDIO_CODEC_I2C_ADDR 0x1A + +/* I2C data hold time */ +#define BOARD_I2C1_DATA_HOLD_TIME 0x1E +#define BOARD_I2C6_DATA_HOLD_TIME 0x1E + +#endif |