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author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-29 01:09:07 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2017-10-15 22:23:01 +0000 |
commit | 81b5bde7e481ab664d581d9c2b17e5b22ac28302 (patch) | |
tree | 93fa34109f0ef2888306235701856cfb47be82e8 /src/mainboard/google/cyan/variants/setzer/romstage.c | |
parent | aa1838577dfdd5eb00e7fffbb4d9246ef2a43aab (diff) |
google/setzer: add new board as variant of cyan baseboard
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/setzer/romstage.c')
-rw-r--r-- | src/mainboard/google/cyan/variants/setzer/romstage.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/setzer/romstage.c b/src/mainboard/google/cyan/variants/setzer/romstage.c new file mode 100644 index 0000000000..13f798924a --- /dev/null +++ b/src/mainboard/google/cyan/variants/setzer/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 4 - 4GiB Micron MT52L256M32D1PF-107 + * RAMID = 5 - 2GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 4 || ram_id == 5) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } +} |