diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-29 00:00:50 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2017-10-13 15:19:44 +0000 |
commit | 35213664cf8f490df3e6b79199774b84f7648d01 (patch) | |
tree | 719602aca8a809314be5a9e3cb42c0d619e7584c /src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl | |
parent | 9681cdc1b495eb88ed33cacdcd37e2393df6c1c4 (diff) |
google/kefka: add new board as variant of cyan baseboard
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram
Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl')
-rw-r--r-- | src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..6f8017960f --- /dev/null +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 68 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 68 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 53 +#define DPTF_TSR2_CRITICAL 66 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 200, 1000, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 200, 1000, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 1000, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 200, 1000, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 200, 1000, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1000, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 2500 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 4500, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 2500 /* StepSize */ + } +}) |