diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-25 01:11:51 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2017-09-21 17:31:29 +0000 |
commit | 6fd2e0e088f678f24554a3e29c25f9d030f2cb66 (patch) | |
tree | 76fb776c6cca6fd042c9156448792fc51ca89b8f /src/mainboard/google/cyan/variants/banon/romstage.c | |
parent | 2f7813f7b3668e67e1ffa7675e53156089a568ef (diff) |
google/banon: add new board as variant of cyan baseboard
Add support for google/banon (Acer Chromebook 15 CB3-531) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new banon variant
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/banon/romstage.c')
-rw-r--r-- | src/mainboard/google/cyan/variants/banon/romstage.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c new file mode 100644 index 0000000000..dab80b0cef --- /dev/null +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 4 - 4GiB Micron MT52L256M32D1PF + * RAMID = 12 - 2GiB Micron MT52L256M32D1PF + */ + if (ram_id == 4 || ram_id == 12) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } + + /* Update SPD data */ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} |