diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-11 17:24:31 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-17 20:24:33 +0200 |
commit | 89b5fbd534fcd1ceab065d293c5a80cdec756675 (patch) | |
tree | 7f597f6092dfbc31552773b76a2d6c80987adc56 /src/mainboard/google/cyan/ramstage.c | |
parent | c42104189bfe3a192c5f1e4b761d7789abee95b3 (diff) |
mainboard/google: Add Braswell based Cyan board
Add initial files for the cyan board.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build
without the FspUpdVpd.h file.
BRANCH=none
BUG=None
Test=Build and run on cyan
Change-Id: I935839be033c25e197e78fbee306104b4162a99a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10182
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/cyan/ramstage.c')
-rw-r--r-- | src/mainboard/google/cyan/ramstage.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c new file mode 100644 index 0000000000..731578542a --- /dev/null +++ b/src/mainboard/google/cyan/ramstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <soc/ramstage.h> +#include <boardid.h> +#include "onboard.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + if (board_id() == BOARD_PRE_EVT) + params->ChvSvidConfig = SVID_CONFIG3; +} |