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authorBalaji Manigandan B <balaji.manigandan@intel.com>2017-12-04 13:24:43 +0530
committerMartin Roth <martinroth@google.com>2017-12-22 16:42:59 +0000
commit361d197d7789f1a974eff05c7a6d7debc0929646 (patch)
treec71f399a3c4a840f55dc2a4c1c91fe0a161ca094 /src/mainboard/google/cyan/fadt.c
parentb8dc63bdfe04fc15553f1ea6e42583cbdaad38ac (diff)
vendor/intel/skykabylake: Update FSP header files to version 2.9.2
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source(s) of PCIe Root Ports. This UPD is used to disable clock source(s) of disabled PCIe Root Port which has active device connected. CQ-DEPEND=CL:*520658,CL:*520659 BUG=b: BRANCH=None TEST= Build and boot soraka Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/22692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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