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author | V Sowmya <v.sowmya@intel.com> | 2020-11-11 06:33:43 +0530 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 01:26:08 +0000 |
commit | 187f06f07e49ed57e0f29de0668113ae03323327 (patch) | |
tree | ddf8659478bf470f82d9a1d6a0a3658d835f966c /src/mainboard/google/cyan/ec.h | |
parent | f7140c425a534341e2f991a1a8b9bd6220602eea (diff) |
soc/intel/common: Add Kconfig for CSE RW firmware version
This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the
CSE RW firmware version from the mainboard. This will be extracted
by makefile to update the cse_rw_metadata structure.
Right now the required tool to extract the CSE RW version from
the blob is still under development and after the official version
of the tool is released, version will be extracted by parsing the
CSE RW blob.
BUG=b:169077783
Cq-Depend: chrome-internal:3402224, chrome-internal:3397863,
chromium:2473603, chromium:2473603, chromium:2535950
Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47430
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/cyan/ec.h')
0 files changed, 0 insertions, 0 deletions