diff options
| author | Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> | 2017-06-05 17:19:26 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-25 19:00:42 +0000 |
| commit | 3d4f04f6b1c802c2c2126b6a6cc97fb5b49ec0bd (patch) | |
| tree | 4360e5871b9f7d773883bc258d3732d5f663f37f /src/mainboard/google/cyan/acpi | |
| parent | 3ff82ca665f643253c9beccfcd83c05933aaa2de (diff) | |
google/cyan: Use GpioInt for Keyboard IRQ
Cherry-pick from Chromium commit a162348.
Remove the hard coded IRQ number for the keyboard interrupt.
IRQ number can change based upon the gpio bank index ordering.
Hence pass the gpio bank and index number so that kernel calculates
the IRQ number.
Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/cyan/acpi')
| -rw-r--r-- | src/mainboard/google/cyan/acpi/superio.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index 34ae34829f..f2a7fc0296 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -23,8 +23,8 @@ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ /* Override default IRQ settings */ -#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ - BOARD_I8042_IRQ} +#define SIO_EC_PS2K_IRQ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,\ + "\\_SB.GPNC") { BOARD_I8042_GPIO_INDEX } /* ACPI code for EC SuperIO functions */ #include <ec/google/chromeec/acpi/superio.asl> |