diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-31 16:45:54 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-02 10:52:45 +0000 |
| commit | 0aa52739dd7ddb6f1f0ca51cef57b8ccd3f0b5b2 (patch) | |
| tree | c8e02a4a535797b41fa24a5d6163608d60a105cc /src/mainboard/google/cyan/acpi/superio.asl | |
| parent | 73b723d7dbb371ec294c5306b8a839cfe93e1bcd (diff) | |
google/cyan: Mark GpioInt() resources as PullDefault
Adapted from chromium commit 3750e09
[Strago: mark GpioInt() resources as PullDefault]
coreboot considers GPIO resources first-class citizens and initializes
all pads according to their intended use, with necessary pull settings
applied. Therefore let's use PullDefault as pull qualifier in AML,
letting the kernel know that it should not attempt to alter pull settings
when using GPIOs.
TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices.
Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/898259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27760
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/cyan/acpi/superio.asl')
| -rw-r--r-- | src/mainboard/google/cyan/acpi/superio.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index ca973d0fab..b3961c00c2 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -23,7 +23,7 @@ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ /* Override default IRQ settings */ -#define SIO_EC_PS2K_IRQ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,\ +#define SIO_EC_PS2K_IRQ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,,\ "\\_SB.GPNC") { BOARD_I8042_GPIO_INDEX } /* ACPI code for EC SuperIO functions */ |