google/cyan: convert to variant configuration

Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:

- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.

- Define the I2C ACPI devices such that they can be easily reused for
other variants.

- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.

- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.

- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.

Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 4 insertions, 59 deletions

diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
index 95b6951279..d0eaadd94f 100644
--- a/src/mainboard/google/cyan/acpi/dptf.asl
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2105 Intel Corp.
+ * Copyright (C) 2015 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,63 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#define DPTF_TSR0_SENSOR_ID	0
-#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
-#define DPTF_TSR0_PASSIVE	49
-#define DPTF_TSR0_CRITICAL	75
+/* Include Variant DPTF */
+#include <variant/acpi/dptf.asl>
 
-#define DPTF_TSR1_SENSOR_ID	1
-#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE	65
-#define DPTF_TSR1_CRITICAL	85
-
-#define DPTF_TSR2_SENSOR_ID	2
-#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE	49
-#define DPTF_TSR2_CRITICAL	75
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
-	Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 },	/* 1.0A (MAX) */
-	Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 },	/* 0.77A */
-	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
-	Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 },	/* 0.25A */
-	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
-})
-
-/* Mainboard specific _PDL is 1GHz */
-Name (MPDL, 8)
-
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 0 */
-	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
-	0x2,		/* Revision */
-	Package () {	/* Power Limit 1 */
-		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		2000,	/* PowerLimitMinimum */
-		6200,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		200	/* StepSize */
-	},
-	Package () {	/* Power Limit 2 */
-		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		8000,	/* PowerLimitMinimum */
-		8000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		1000	/* StepSize */
-	}
-})
-
-/* Include DPTF */
+/* Include SoC DPTF */
 #include <acpi/dptf/dptf.asl>