diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-03 14:25:46 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-12-09 11:55:03 +0000 |
| commit | 76c426ab285bc1a3c65305704575a1a165c396b5 (patch) | |
| tree | df83ae609f3227afdfde63d9c6ba9d5ffd12bc0d /src/mainboard/google/corsola | |
| parent | 9f6805afe8d014f4a8fe2d3a342221b2c62f15df (diff) | |
mb/google/corsola: correct NOR flash configuration in GPIO set
The reference design has changed to use GPIO SET1 for NOR flash.
There are no devices already built using SET0 so we can safely
change the implementation without conditional configs.
Reference document:
kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11.
crab_proto 0_2021112.pdf, page 11.
BUG=b:202871018
TEST=flash verify pass on kingler on bootblock stage
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/google/corsola')
| -rw-r--r-- | src/mainboard/google/corsola/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index ea36fed93b..0b03d048f4 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -10,7 +10,7 @@ void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); - mtk_snfc_init(SPI_NOR_GPIO_SET0); + mtk_snfc_init(SPI_NOR_GPIO_SET1); setup_chromeos_gpios(); gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING); } |