diff options
author | V Sowmya <v.sowmya@intel.com> | 2020-06-17 16:17:19 +0530 |
---|---|---|
committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-07-23 04:54:01 +0000 |
commit | e8156ad9818111a58e0d54e27b74e083c1d4f856 (patch) | |
tree | bb7479c44efda11254caec3803085a48d8af2d6c /src/mainboard/google/cheza/reset.c | |
parent | df96d4db84f192e6d3e21f4995d548af84e1df5e (diff) |
soc/intel/jasperlake: Add the SkipCpuReplacementCheck configuration
Add SkipCpuReplacementCheck config to control the FSPM UPD used
for skipping the CPU replacementment check to avoid the forced
MRC training for the platforms with soldered down SOC.
BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddleddo.
Cq-Depend: chrome-internal:3142530
Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/mainboard/google/cheza/reset.c')
0 files changed, 0 insertions, 0 deletions