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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-06-12 02:47:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-21 08:12:33 +0000 |
| commit | 5a401ae26215ee2fdb63e9b2d5e49f2df528979e (patch) | |
| tree | 3ec8a7644f5092532a310d885c7f0cafd5655540 /src/mainboard/google/cheza/bootblock.c | |
| parent | 388e551dc3d558f82804c144059ac2eb6df7d27c (diff) | |
mb/intel/tglrvp: Enable HECI interface
This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.
BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/cheza/bootblock.c')
0 files changed, 0 insertions, 0 deletions