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| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-04-06 14:10:53 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-10 05:28:19 +0000 |
| commit | 4b97a134857f98c4c0378ab0118b75b5b6a482dc (patch) | |
| tree | fb8c9695cbe0c96eae506a35c70177bf5266168c /src/mainboard/google/cherry/Kconfig | |
| parent | 19a1bad42597c939dbd0ce9eabe8d610d3f7e2c2 (diff) | |
mb/google/cherry: Configure TPM
Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/cherry/Kconfig')
| -rw-r--r-- | src/mainboard/google/cherry/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index b9c63ea9e6..7377c6c94a 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_I2C_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT config MAINBOARD_DIR string @@ -31,6 +33,14 @@ config MAINBOARD_PART_NUMBER string default "Cherry" if BOARD_GOOGLE_CHERRY +config DRIVER_TPM_I2C_BUS + hex + default 0x3 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + # On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus. # The number here should be a virtual value as (SPI_BUS_NUMBER + 1). config BOOT_DEVICE_SPI_FLASH_BUS |