skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI

Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 16 insertions, 16 deletions

diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h
index 6f30e1e849..76b2d09cc8 100644
--- a/src/mainboard/google/chell/gpio.h
+++ b/src/mainboard/google/chell/gpio.h
@@ -106,23 +106,23 @@ static const struct pad_config gpio_table[] = {
 /* GSPI1_CLK */		PAD_CFG_NC(GPP_B20),
 /* GSPI1_MISO */	PAD_CFG_NC(GPP_B21),
 /* GSPI1_MOSI */	PAD_CFG_GPO(GPP_B22, 0, DEEP),
-/* SM1ALERT# */		PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */
+/* SM1ALERT# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */
 /* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
 /* SMBALERT# */		PAD_CFG_GPO(GPP_C2, 0, DEEP),
-/* SML0CLK */		PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */
-/* SML0DATA */		PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */
-/* SML0ALERT# */	PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */		PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */
+/* SML0CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */
+/* SML0DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */
+/* SML0ALERT# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */
 /* UART0_RXD */		PAD_CFG_NC(GPP_C8),
 /* UART0_TXD */		PAD_CFG_NC(GPP_C9),
 /* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
+/* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
+/* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
+/* UART1_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
+/* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
@@ -130,7 +130,7 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
 /* SPI1_CS# */		PAD_CFG_GPO(GPP_D0, 0, DEEP),
 /* SPI1_CLK */		PAD_CFG_GPO(GPP_D1, 0, DEEP),
 /* SPI1_MISO */		PAD_CFG_GPO(GPP_D2, 0, DEEP),
@@ -184,10 +184,10 @@ static const struct pad_config gpio_table[] = {
  * together with i2s0 signals. For default behavior of i2s make these
  * gpio inupts.
  */
-/* I2S2_SCLK */		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */		PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+/* I2S2_SCLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		PAD_CFG_NC(GPP_F4),
 /* I2C2_SCL */		PAD_CFG_NC(GPP_F5),
 /* I2C3_SDA */		PAD_CFG_NC(GPP_F6),
@@ -234,7 +234,7 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
 };
 
 #endif