diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-02-25 08:53:40 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-29 20:58:24 +0100 |
| commit | 4815fb8dc5eb7b44bc8aa2a981c6a6bee55fa5c7 (patch) | |
| tree | a4cf145220e3e21368ff199a3614e6f96dbae1bf /src/mainboard/google/chell | |
| parent | e355ee26b806c3cf7dd342dd51e2d60f2b7cdc9b (diff) | |
google/chell: Update GPIOs for DVT2
Add new GPIOs for touchscreen enable and reset pins and define
the one missing unconnected pin for GPP_E10.
BUG=chrome-os-partner:50518
BRANCH=glados
TEST=build and boot on chell DVT1
Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d
Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329297
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13841
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/chell')
| -rw-r--r-- | src/mainboard/google/chell/gpio.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 01b4e3157d..0503e3e768 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ @@ -158,14 +158,14 @@ static const struct pad_config gpio_table[] = { /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ /* GPP_E10 */ +/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ |