diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-11 07:46:50 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-12 18:03:23 +0100 |
| commit | 6d6298dddc4147e7a1df6c51cb97b3d94e9c4584 (patch) | |
| tree | e51953d0c3691a6ae4ff491981d7e77f0d3aff7a /src/mainboard/google/butterfly | |
| parent | 2dd601efafb54433e1bbf60f3936eeba7ef353e2 (diff) | |
ibexpeak / bd82x6x: Make SATA mode user-visible option.
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.
As per comments
"ide_legacy_combined # TODO: Does nothing since
generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.
Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/butterfly')
| -rw-r--r-- | src/mainboard/google/butterfly/cmos.layout | 5 | ||||
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624705..ee5ee256c1 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index e7a50c0c57..9a7a1d571e 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -56,8 +56,6 @@ chip northbridge/intel/sandybridge #register "gpi1_routing" = "1" #SMI from EC register "gpi13_routing" = "2" #SCI from EC - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s |