diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-02-06 17:42:42 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-18 01:35:57 +0100 |
| commit | e8e66f47631c505ab153d8a348058350b9acfe88 (patch) | |
| tree | 535bc168855923222affbf6bdb06620cbd8fb343 /src/mainboard/google/butterfly | |
| parent | ffc31d07f7839fa72073aae4ddbbd025ac4a7bac (diff) | |
southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/butterfly')
| -rw-r--r-- | src/mainboard/google/butterfly/chromeos.c | 37 | ||||
| -rw-r--r-- | src/mainboard/google/butterfly/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/butterfly/romstage.c | 2 |
3 files changed, 5 insertions, 36 deletions
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 0b750b129a..69887f5a68 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -21,6 +21,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> #include <ec/quanta/ene_kb3940q/ec.h> #include "ec.h" @@ -29,9 +30,6 @@ #define FORCE_RECOVERY_MODE 0 #define FORCE_DEVELOPER_MODE 0 - -int get_pch_gpio(unsigned char gpio_num); - #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -92,38 +90,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif -int get_pch_gpio(unsigned char gpio_num) -{ - device_t dev; - int retval = 0; - -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); -#endif - u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; - - if (!gpio_base) - return(0); - - if (gpio_num >= 64){ - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - retval = ((gp_lvl3 >> (gpio_num - 64)) & 1); - } else if (gpio_num >= 32){ - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - retval = ((gp_lvl2 >> (gpio_num - 32)) & 1); - } else { - u32 gp_lvl = inl(gpio_base + GP_LVL); - retval = ((gp_lvl >> gpio_num) & 1); - } - - return retval; -} - int get_write_protect_state(void) { - return !get_pch_gpio(WP_GPIO); + return !get_gpio(WP_GPIO); } int get_lid_switch(void) @@ -141,7 +110,7 @@ int get_developer_mode_switch(void) #endif /* Servo GPIO is active low, reverse it for intial state (request) */ - dev_mode = !get_pch_gpio(DEVMODE_GPIO); + dev_mode = !get_gpio(DEVMODE_GPIO); printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO, dev_mode); diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c index a08b787fb8..2d14699ef6 100644 --- a/src/mainboard/google/butterfly/gpio.c +++ b/src/mainboard/google/butterfly/gpio.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* Unused */ diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index a5aa793c16..050d5b0fd4 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -30,7 +30,7 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> |