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authorNico Huber <nico.h@gmx.de>2019-11-17 01:24:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:50:15 +0000
commite036aaede49c3add3b1d9ce6ef7ae7f849b0683f (patch)
tree9e865c79b11d3749e176d81c9b9e3211e7052523 /src/mainboard/google/butterfly
parent3ad93615be8ac71308bdaa90a5ddd6ed57a304a1 (diff)
mb/google(sandybrige): Clean up LPC and IOAPIC configuration
Only set LPC decode bits that the generic PCH code doesn't set yet. And don't enable the IOAPIC, which is already done by generic code. Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/google/butterfly')
-rw-r--r--src/mainboard/google/butterfly/early_init.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index d6566d1b09..19910bac99 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -28,13 +28,6 @@
#include <vendorcode/google/chromeos/chromeos.h>
#endif
-void mainboard_pch_lpc_setup(void)
-{
- /* EC Decode Range Port60/64 and Port62/66 */
- /* Enable EC and PS/2 Keyboard/Mouse*/
- pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
-}
-
void mainboard_late_rcba_config(void)
{
u32 reg32;
@@ -76,11 +69,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
-
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */