diff options
| author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2022-06-21 16:22:07 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-24 13:27:31 +0000 |
| commit | fe5ad028a4330619ef090146e969514e970a3ccc (patch) | |
| tree | 7bff4587cb505602e06d8cf7d70faab42179bc8d /src/mainboard/google/brya | |
| parent | bbf794fc13a5be6445aff7dcc9430ef7152f9148 (diff) | |
mb/google/nissa/var/xivu: Update gpio settings
Configure GPIOs according to schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8c4347fcc975ed994261c7738e5ef811a12e4b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/xivu/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/xivu/gpio.c | 68 |
2 files changed, 72 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/xivu/Makefile.inc b/src/mainboard/google/brya/variants/xivu/Makefile.inc new file mode 100644 index 0000000000..3939ec138f --- /dev/null +++ b/src/mainboard/google/brya/variants/xivu/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/xivu/gpio.c b/src/mainboard/google/brya/variants/xivu/gpio.c new file mode 100644 index 0000000000..d154af8fdb --- /dev/null +++ b/src/mainboard/google/brya/variants/xivu/gpio.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |