diff options
| author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2024-04-02 08:57:43 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-11 12:16:39 +0000 |
| commit | 5eecafe89ea34f035dc310b89e6f77c5e55e1b64 (patch) | |
| tree | c510e5850a1a4671630507718be6db90406cb069 /src/mainboard/google/brya | |
| parent | 2abfbb4b879c2251f413dcd36373db411e6c2965 (diff) | |
mb/google/nissa/var/craaskov: Disable external fivr
In next phase, craaskov will remove external fivr. Use the board
version to config external fivr for backward compatibility and
show message.
BUG=b:330253778
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/craaskov/overridetree.cb | 15 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craaskov/variant.c | 26 |
2 files changed, 26 insertions, 15 deletions
diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index 686c829349..eee54026fe 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -60,21 +60,6 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - # Configure external V1P05/Vnn/VnnSx Rails - register "ext_fivr_settings" = "{ - .configure_ext_fivr = 1, - .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, - .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, - .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, - .v1p05_voltage_mv = 1050, - .vnn_voltage_mv = 780, - .vnn_sx_voltage_mv = 1050, - .v1p05_icc_max_ma = 500, - .vnn_icc_max_ma = 500, - }" - register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, diff --git a/src/mainboard/google/brya/variants/craaskov/variant.c b/src/mainboard/google/brya/variants/craaskov/variant.c index 68f128c7d7..cee0308aaa 100644 --- a/src/mainboard/google/brya/variants/craaskov/variant.c +++ b/src/mainboard/google/brya/variants/craaskov/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <boardid.h> #include <device/device.h> #include <sar.h> @@ -31,3 +32,28 @@ void variant_devtree_update(void) ish->enabled = 0; } } + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + const uint32_t id = board_id(); + if (id == BOARD_ID_UNKNOWN || id < 2) { // proto=0, EVT=1 + config->ext_fivr_settings.configure_ext_fivr = 1; + + config->ext_fivr_settings.v1p05_enable_bitmap = + FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0; + config->ext_fivr_settings.vnn_enable_bitmap = + FIVR_ENABLE_ALL_SX; + config->ext_fivr_settings.vnn_sx_enable_bitmap = + FIVR_ENABLE_ALL_SX; + config->ext_fivr_settings.v1p05_supported_voltage_bitmap = + FIVR_VOLTAGE_NORMAL; + config->ext_fivr_settings.vnn_supported_voltage_bitmap = + FIVR_VOLTAGE_MIN_ACTIVE; + config->ext_fivr_settings.v1p05_voltage_mv = 1050; + config->ext_fivr_settings.vnn_voltage_mv = 780; + config->ext_fivr_settings.vnn_sx_voltage_mv = 1050; + config->ext_fivr_settings.v1p05_icc_max_ma = 500; + config->ext_fivr_settings.vnn_icc_max_ma = 500; + printk(BIOS_INFO, "Configured external FIVR\n"); + } +} |