diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2022-01-28 16:07:28 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-02 13:25:35 +0000 |
| commit | 57fc1b91b935cf1984d87690221d6f87b9942cbf (patch) | |
| tree | 7148137a6fac61d2bcc927319de09a2d5d5ccd54 /src/mainboard/google/brya | |
| parent | 5a49f3aa7973cce8936bfe6600d2726904d24947 (diff) | |
mb/google/brya/var/vell: Enable SaGv
This patch enables SaGv since somehow it was accidently removed
by commit a52b9c3.
BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot
Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya
variants to baseboards")
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index ed2ccd7765..4daf446f64 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -50,6 +50,7 @@ chip soc/intel/alderlake }, }" register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 + register "SaGv" = "SaGv_Enabled" # I2C Port Config register "SerialIoI2cMode" = "{ |