mb/google/brya: Add new skolas baseboard

This commit adds the skolas baseboard, which is basically the brya
baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder
Lake SoC.

This commit also adds the skolas baseboard variant skolas4es.

Since this baseboard is identical to the brya baseboard with the
exception of the SoC used, the new baseboard and the new baseboard's
first variant will be a copy of the current brya baseboard and brya0
variant.

For now, the skolas baseboard and skolas4es variant will continue to
use ADL-P.  This allows for two benefits:
  1. software to be proven out on existing hardware prior to RPL SoC
	support landing, and
  2. allows us not to have to wait for RPL SoC changes prior to getting
	the mainboard changes in place

Once the RPL SoC code has merged, I will update the skolas baseboard and
skolas4es variant to use RPL instead of ADL.

BUG=b:229134437
TEST=util/abuild/abuild -p none -t google/brya -x -a -c max

Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

20 files changed, 2176 insertions, 1 deletions

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index cd45164fc7..1f3b3d5b53 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -73,6 +73,15 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select TPM_GOOGLE_TI50
 	select SOC_INTEL_COMMON_MMC_OVERRIDE
 
+config BOARD_GOOGLE_BASEBOARD_SKOLAS
+	def_bool n
+	select BOARD_GOOGLE_BRYA_COMMON
+	select HAVE_SLP_S0_GATE
+	select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_GOOGLE_CR50
+
 if BOARD_GOOGLE_BRYA_COMMON
 
 config BASEBOARD_DIR
@@ -80,6 +89,7 @@ config BASEBOARD_DIR
 	default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA
 	default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 	default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
+	default "skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -127,6 +137,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_OSIRIS
 	default 0x1 if BOARD_GOOGLE_MITHRAX
 	default 0x1 if BOARD_GOOGLE_KULDAX
+	default 0x3 if BOARD_GOOGLE_SKOLAS4ES
 
 config DRIVER_TPM_I2C_ADDR
 	hex
@@ -153,6 +164,7 @@ config MAINBOARD_FAMILY
 	default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA
 	default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 	default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
+	default "Google_Skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS
 
 config MAINBOARD_PART_NUMBER
 	default "Brya" if BOARD_GOOGLE_BRYA0
@@ -184,6 +196,7 @@ config MAINBOARD_PART_NUMBER
 	default "Osiris" if BOARD_GOOGLE_OSIRIS
 	default "Mithrax" if BOARD_GOOGLE_MITHRAX
 	default "Kuldax" if BOARD_GOOGLE_KULDAX
+	default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES
 
 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
@@ -215,6 +228,7 @@ config VARIANT_DIR
 	default "osiris" if BOARD_GOOGLE_OSIRIS
 	default "mithrax" if BOARD_GOOGLE_MITHRAX
 	default "kuldax" if BOARD_GOOGLE_KULDAX
+	default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
@@ -245,7 +259,7 @@ config USE_PM_ACPI_TIMER
 
 choice
 	prompt "Cache as RAM (CAR) setup configuration to use"
-	default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK
+	default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS4ES
 	default USE_ADL_ENEM
 
 config USE_ADL_ENEM
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 62aa03878d..70ee5a84dd 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -138,6 +138,13 @@ config BOARD_GOOGLE_REDRIX4ES
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_IPU
 
+config BOARD_GOOGLE_SKOLAS4ES
+	bool "->  Skolas4ES"
+	select BOARD_GOOGLE_BASEBOARD_SKOLAS
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select SOC_INTEL_COMMON_BLOCK_IPU
+
 config BOARD_GOOGLE_TAEKO
 	bool "->  Taeko"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc
new file mode 100644
index 0000000000..8a4b2acfaa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
new file mode 100644
index 0000000000..f2276d0447
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
@@ -0,0 +1,175 @@
+chip soc/intel/alderlake
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_E"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	# S0ix enable
+	register "s0ix_enable" = "1"
+
+	# DPTF enable
+	register "dptf_enable" = "1"
+
+	register "tcc_offset" = "10"     # TCC of 90
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
+	register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
+	register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
+	register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	# FIVR RFI Spread Spectrum 1.5%
+	register "fivr_spread_spectrum" = "FIVR_SS_1_5"
+
+	# Disable C state auto-demotion for all brya baseboards
+	register "disable_c1_state_auto_demotion" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio and WFC             |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | SAR0                      |
+	#| I2C3              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 900,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+	}"
+
+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
+	device domain 0 on
+		device ref igpu on end
+		device ref dtt on end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tcss_xhci on end
+		device ref tcss_dma0 on end
+		device ref tcss_dma1 on end
+		device ref xhci on end
+		device ref shared_sram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "is_untrusted" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref i2c3 on end
+		device ref heci1 on end
+		device ref sata on end
+		device ref pcie_rp8 on
+			# Enable SD Card PCIE 8 using clk 3
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			# Enable NVMe PCIE 9 using clk 1
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE9-12 SSD
+		device ref uart0 on end
+		device ref gspi1 on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref hda on end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c b/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c
new file mode 100644
index 0000000000..fb7bc21d2d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c
@@ -0,0 +1,454 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <types.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_IO_0 */
+	/* A1  : ESPI_IO1 ==> ESPI_IO_1 */
+	/* A2  : ESPI_IO2 ==> ESPI_IO_2 */
+	/* A3  : ESPI_IO3 ==> ESPI_IO_3 */
+	/* A4  : ESPI_CS# ==> ESPI_CS_L */
+	/* A5  : ESPI_ALERT0# ==> NC */
+	PAD_NC(GPP_A5, NONE),
+	/* A6  : ESPI_ALERT1# ==> SPKR_INT_L */
+	PAD_CFG_GPI(GPP_A6, NONE, DEEP),
+	/* A7  : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT),
+	/* A8  : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A9  : ESPI_CLK ==> ESPI_CLK */
+	/* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
+	/* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_A11, 1, DEEP),
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* A14 : USB_OC1# ==> USB_C1_OC_ODL */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : USB_OC3# ==> USB_A0_OC_ODL */
+	PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG),
+	/* A17 : DISP_MISCC ==> EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+	/* A18 : DDSP_HPDB ==> HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6),
+	/* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6),
+	/* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
+	/* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+	/* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
+
+	/* B0  : SOC_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : SOC_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2  : VRALERT# ==> M2_SSD_PLA_L */
+	PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG),
+	/* B3  : PROC_GP2 ==> SAR2_INT_L */
+	PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
+	/* B5  : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */
+	PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
+	/* B6  : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */
+	PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+	/* B9  : NC */
+	PAD_NC(GPP_B9, NONE),
+	/* B10 : NC */
+	PAD_NC(GPP_B10, NONE),
+	/* B11 : PMCALERT# ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_B11, 1, DEEP),
+	/* B12 : SLP_S0# ==> SLP_S0_L */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLTRST# ==> PLT_RST_L */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14 : SPKR ==> GPP_B14_STRAP */
+	PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
+	/* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
+	PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG),
+	/* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
+	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
+	/* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
+	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
+	/* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
+	PAD_NC(GPP_B18, NONE),
+	/* B19 : NC */
+	PAD_NC(GPP_B19, NONE),
+	/* B20 : NC */
+	PAD_NC(GPP_B20, NONE),
+	/* B21 : NC */
+	PAD_NC(GPP_B21, NONE),
+	/* B22 : NC */
+	PAD_NC(GPP_B22, NONE),
+	/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, NONE),
+	/* C3 : SML0CLK ==> EN_UCAM_PWR */
+	PAD_CFG_GPO(GPP_C3, 0, DEEP),
+	/* C4 : SML0DATA ==> EN_UCAM_SENR_PWR */
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+	/* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : SML1CLK ==> USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_C6, 0, DEEP),
+	/* C7  : SML1DATA ==> USI_INT */
+	PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
+
+	/* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
+	PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> WCAM_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
+	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_D4, 1, DEEP),
+	/* D5  : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */
+	PAD_CFG_GPO(GPP_D5, 1, DEEP),
+	/* D6  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D9  : ISH_SPI_CS# ==> USB_C2_LSX_TX */
+	PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG),
+	/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
+	PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
+	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
+	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
+	/* D13 : ISH_UART0_RXD ==> CAM_PSW_L */
+	PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG),
+	/* D14 : ISH_UART0_TXD ==> SPKR_INT_L */
+	PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG),
+	/* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
+	PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
+	/* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
+	PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
+	/* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
+	PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* D18 : UART1_TXD ==> SD_PE_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
+	/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* E0  : see end of E group */
+	/* E1  : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
+	PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
+	/* E2  : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
+	PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
+	/* E3  : PROC_GP0 ==> HPS_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE),
+	/* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	/* E5  : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
+	PAD_CFG_GPO(GPP_E5, 1, DEEP),
+	/* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
+	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
+	/* E7  : PROC_GP1 ==> EN_HPS_PWR */
+	PAD_CFG_GPO(GPP_E7, 1, DEEP),
+	/* E8  : SLP_DRAM# ==> WIFI_DISABLE_L */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
+	/* E9  : USB_OC0# ==> USB_C0_OC_ODL */
+	PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
+	/* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */
+	PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG),
+	/* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */
+	PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG),
+	/* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */
+	PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
+	/* E16 : RSVD_TP ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */
+	PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
+	/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	/* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	/* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+	/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
+	/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
+	/* E0 : SATAXPCIE0 ==> WWAN_PERST_L
+	   NB. Driven high here so that it is sequenced after WWAN_RST_L; a
+	   PERST# signal would normally be reset by PLRST#, but here it will be
+	   explicitly programmed during a power-down sequence. */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),
+
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : MODEM_CLKREQ ==> CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+	/* F6  : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F7  : GPPF7_STRAP */
+	PAD_NC(GPP_F7, NONE),
+	/* F8  : NC */
+	PAD_NC(GPP_F8, NONE),
+	/* F9  : BOOTMPC ==> SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_F9, 1, PLTRST),
+	/* F10 : GPPF10_STRAP */
+	PAD_NC(GPP_F10, DN_20K),
+	/* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
+	PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
+	PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
+	/* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
+	PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
+	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> FPMCU_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
+	PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
+	/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
+	/* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */
+	PAD_CFG_GPO(GPP_F19, 1, PLTRST),
+	/* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* F22 : NC */
+	PAD_NC(GPP_F22, NONE),
+	/* F23 : NC */
+	PAD_NC(GPP_F23, NONE),
+
+	/* H0  : GPPH0_BOOT_STRAP1 */
+	PAD_NC(GPP_H0, NONE),
+	/* H1  : GPPH1_BOOT_STRAP2 */
+	PAD_NC(GPP_H1, NONE),
+	/* H2  : GPPH2_BOOT_STRAP3 */
+	PAD_NC(GPP_H2, NONE),
+	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG),
+	/* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8  : I2C4_SDA ==> WWAN_WLAN_COEX1 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9  : I2C4_SCL ==> WWAN_WLAN_COEX2 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG),
+	/* H14 : NC */
+	PAD_NC(GPP_H14, NONE),
+	/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H16 : NC */
+	PAD_NC(GPP_H16, NONE),
+	/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : SRCCLKREQ4# ==> SAR1_INT_L */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+	/* H21 : IMGCLKOUT2 ==>  UCAM_MCLK */
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
+
+	/* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
+	/* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+	/* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	/* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+	/* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+	/* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+	/* S2 : SNDW1_CLK ==> DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
+	/* S3 : SNDW1_DATA ==> DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
+	/* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
+	/* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
+	/* S6 : SNDW3_CLK ==> DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* S7 : SNDW3_DATA ==> DMIC_DATA1_R */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* GPD0: BATLOW# ==> BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1: ACPRESENT ==> PCH_ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+	/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+	/* GPD4: SLP_S3# ==> SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5: SLP_S4# ==> SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6: SLP_A# ==> SLP_A_L */
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	/* GPD7: GPD7_STRAP */
+	PAD_NC(GPD7, NONE),
+	/* GPD8: SUSCLK ==> PCH_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* GPD10: SLP_S5# ==> SLP_S5_L */
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	/* GPD11: LANPHYC ==> WWAN_CONFIG1 */
+	PAD_CFG_GPI(GPD11, NONE, DEEP),
+
+	/* Virtual GPIO */
+	/* Put unused Cnvi BT UART lines in NC mode since we use USB mode. */
+	PAD_NC(GPP_VGPIO_6, NONE),
+	PAD_NC(GPP_VGPIO_7, NONE),
+	PAD_NC(GPP_VGPIO_8, NONE),
+	PAD_NC(GPP_VGPIO_9, NONE),
+
+	/* Put unused Cnvi UART0 lines in NC mode since we use USB mode. */
+	PAD_NC(GPP_VGPIO_18, NONE),
+	PAD_NC(GPP_VGPIO_19, NONE),
+	PAD_NC(GPP_VGPIO_20, NONE),
+	PAD_NC(GPP_VGPIO_21, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L
+	 * To meet timing constrains - drive reset low.
+	 * Deasserted in ramstage.
+	 */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);
+
+const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h
new file mode 100644
index 0000000000..3c7fde5f54
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/*
+ * EC can wake from S3/S0ix with:
+ * 1. Lid open
+ * 2. AC Connect/Disconnect
+ * 3. Power button
+ * 4. Key press
+ * 5. Mode change
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(MAINBOARD_EC_S3_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)         |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+/*
+ * ACPI related definitions for ASL code.
+ */
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+/* Enable Keyboard Backlight */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+#define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h
new file mode 100644
index 0000000000..0de7ffd36c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
+#define GPE_EC_WAKE		GPE0_DW2_17
+/* WP signal to PCH */
+#define GPIO_PCH_WP		GPP_E15
+/* EC in RW or RO */
+#define GPIO_EC_IN_RW		GPP_F18
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_F9
+/* GPIO IRQ for tight timestamps / wake support */
+#define EC_SYNC_IRQ		GPP_F17_IRQ
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/memory.c b/src/mainboard/google/brya/variants/baseboard/skolas/memory.c
new file mode 100644
index 0000000000..bcad9b4be9
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/memory.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
+			.dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
+		},
+		.ddr1 = {
+			.dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
+			.dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
+			.dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
+			.dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
+		},
+		.ddr4 = {
+			.dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
+			.dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
+		},
+		.ddr5 = {
+			.dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
+			.dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
+		},
+		.ddr6 = {
+			.dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
+			.dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
+			.dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E11
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E1
+	 * GPIO_MEM_CONFIG_3	GPP_E12
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E11,
+		GPP_E2,
+		GPP_E1,
+		GPP_E12,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_E13 */
+	return gpio_get(GPP_E13);
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c b/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c
new file mode 100644
index 0000000000..9c2d4aa0b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi_device.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+
+#include <drivers/intel/dptf/chip.h>
+#include <intelblocks/power_limit.h>
+
+WEAK_DEV_PTR(dptf_policy);
+
+void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
+{
+	if (!num_entries)
+		return;
+
+	const struct device *policy_dev = DEV_PTR(dptf_policy);
+	if (!policy_dev)
+		return;
+
+	struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+
+	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+
+	u8 tdp = get_cpu_tdp();
+
+	for (size_t i = 0; i < num_entries; i++) {
+		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
+			struct dptf_power_limits *settings = &config->controls.power_limits;
+			config_t *conf = config_of_soc();
+			struct soc_power_limits_config *soc_config = conf->power_limits_config;
+			settings->pl1.min_power = limits[i].pl1_min_power;
+			settings->pl1.max_power = limits[i].pl1_max_power;
+			settings->pl2.min_power = limits[i].pl2_min_power;
+			settings->pl2.max_power = limits[i].pl2_max_power;
+			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
+							   MILLIWATTS_TO_WATTS);
+			printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
+					limits[i].pl1_min_power,
+					limits[i].pl1_max_power,
+					limits[i].pl2_min_power,
+					limits[i].pl2_max_power,
+					limits[i].pl4_power);
+		}
+	}
+}
diff --git a/src/mainboard/google/brya/variants/skolas4es/Makefile.inc b/src/mainboard/google/brya/variants/skolas4es/Makefile.inc
new file mode 100644
index 0000000000..52d03980da
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/skolas4es/fw_config.c b/src/mainboard/google/brya/variants/skolas4es/fw_config.c
new file mode 100644
index 0000000000..c2b963fe22
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/fw_config.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),	/* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),	/* DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+};
+
+static const struct pad_config sndw_enable_pads[] = {
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),	/* SDW_HP_CLK_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),	/* SDW_HP_DATA_R */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),	/* SDW_SPKR_CLK */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),	/* SDW_SPKR_DATA */
+};
+
+static const struct pad_config max98360_enable_pads[] = {
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),    /* I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),    /* I2S_PCH_RX_SPKR_TX */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),    /* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),    /* DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),    /* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),    /* DMIC_DATA1_R */
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config sndw_disable_pads[] = {
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+};
+
+static const struct pad_config i2s0_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+};
+
+static const struct pad_config i2s2_enable_pads[] = {
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),	/* I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),	/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s0_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+};
+
+static const struct pad_config i2s2_disable_pads[] = {
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void enable_i2s(void)
+{
+	gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+	gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
+	gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads));
+	gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
+}
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
+		gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) {
+		printk(BIOS_INFO, "Configure audio over SoundWire with MAX98373 ALC5682.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
+		gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	} else if (!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "BT offload disabled\n");
+		gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
+		gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n");
+		enable_i2s();
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, ALC1019_NAU88L25B_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n");
+		enable_i2s();
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
+		gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/skolas4es/gpio.c b/src/mainboard/google/brya/variants/skolas4es/gpio.c
new file mode 100644
index 0000000000..251348beaa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/gpio.c
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+static const struct pad_config board_id0_1_overrides[] = {
+	/* B2  : VRALERT# ==> NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+	/* B15 : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+	/* C3  : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4  : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+	/* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
+	/* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
+	/* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
+	PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
+	/* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
+	PAD_NC(GPP_F21, NONE),
+	/* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
+	PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
+	/* GPD2: LAN_WAKE# ==> NC */
+	PAD_NC(GPD2, NONE),
+};
+
+/* Early pad configuration in bootblock for board id < 2 */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+/* Early pad configuration in bootblock for board id 2 */
+static const struct pad_config early_gpio_table_id2[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+/* Early pad configuration in bootblock for board id 4 */
+static const struct pad_config early_gpio_table_id4[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* H6  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external
+	 * pull-down. To ensure proper power sequencing for the FPMCU device,
+	 * reset signal is driven low early on in bootblock, followed by
+	 * enabling of power. Reset signal is deasserted later on in ramstage.
+	 * Since reset signal is asserted in bootblock, it results in FPMCU not
+	 * working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(board_id0_1_overrides);
+		return board_id0_1_overrides;
+	}
+
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(early_gpio_table);
+		return early_gpio_table;
+	} else if (id >= 4) {
+		*num = ARRAY_SIZE(early_gpio_table_id4);
+		return early_gpio_table_id4;
+	}
+
+	*num = ARRAY_SIZE(early_gpio_table_id2);
+	return early_gpio_table_id2;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/skolas4es/include/variant/ec.h b/src/mainboard/google/brya/variants/skolas4es/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/brya/variants/skolas4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/skolas4es/include/variant/gpio.h
new file mode 100644
index 0000000000..23338de2d8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/include/variant/gpio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_E16
+#define WWAN_PERST	GPP_E0
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/skolas4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/skolas4es/memory/Makefile.inc
new file mode 100644
index 0000000000..e930ba212c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/memory/Makefile.inc
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/skolas4es/memory src/mainboard/google/brya/variants/skolas4es/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = MT53E2G32D4NQ-046 WT:A
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/skolas4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/skolas4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..01b197a4de
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/memory/dram_id.generated.txt
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/skolas4es/memory src/mainboard/google/brya/variants/skolas4es/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:F       0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E1G32D2NP-046 WT:A         1 (0001)
+MT53E2G32D4NQ-046 WT:A         2 (0010)
+H9HCNNNCPMMLXR-NEE             3 (0011)
+MT53E1G32D2NP-046 WT:B         3 (0011)
diff --git a/src/mainboard/google/brya/variants/skolas4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/skolas4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..c8a24ccd6d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/memory/mem_parts_used.txt
@@ -0,0 +1,6 @@
+MT53E512M32D2NP-046 WT:F
+H9HCNNNBKMMLXR-NEE
+MT53E1G32D2NP-046 WT:A
+MT53E2G32D4NQ-046 WT:A
+H9HCNNNCPMMLXR-NEE
+MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
new file mode 100644
index 0000000000..6f0eb2168e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -0,0 +1,827 @@
+fw_config
+	field DB_USB 0 3
+		option USB_ABSENT		0
+		option USB3_PS8815		1
+	end
+	field DB_SD 4 5
+		option SD_ABSENT		0
+		option SD_GL9755S		1
+	end
+	field KB_BL 7 7
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field AUDIO 8 10
+		option AUDIO_UNKNOWN			0
+		option MAX98357_ALC5682I_I2S		1
+		option MAX98373_ALC5682_SNDW		2
+		option MAX98373_NAU88L25B_I2S		3
+		option ALC1019_NAU88L25B_I2S		4
+		option MAX98360_ALC5682I_I2S		5
+	end
+	field DB_LTE 11 12
+		option LTE_ABSENT		0
+		option LTE_USB			1
+		option LTE_PCIE			2
+	end
+	field UFC 13 14
+		option UFC_USB			0
+		option UFC_MIPI_IMX208		1
+	end
+	# Bits 15 and 16 were intended for WFC but never declared here
+	field HPS 17 17
+		option HPS_ABSENT               0
+		option HPS_PRESENT              1
+	end
+end
+
+chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	register "platform_pmax" = "145"
+
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A MLB Port
+
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
+	# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
+	# bypass rails implemented.
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C2              | SAR                       |
+	#| I2C3              | TouchScreen               |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[1] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 900,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""WWAN""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+								TEMP_PCT(70, 50),
+								TEMP_PCT(65, 30),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_1,
+						.thresholds = {
+								TEMP_PCT(50, 90),
+								TEMP_PCT(48, 70),
+								TEMP_PCT(46, 60),
+								TEMP_PCT(43, 40),
+								TEMP_PCT(40, 30),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 75, 5000),
+					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
+				register "cio2_prt[0]" = "2"
+				device generic 0 on
+					# MIPI lanes are split between UFC and WFC depending on
+					# whether the UFC is USB or MIPI hence probing UFC_USB
+					probe UFC UFC_USB
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "2"
+				register "cio2_prt[1]" = "1"
+				device generic 1 on
+					probe UFC UFC_MIPI_IMX208
+				end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# Enable WWAN PCIE 6 using clk 5
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "reset_off_delay_ms" = "20"
+				# register "reset_delay_ms" = "1000"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				device generic 0 alias rp6_rtd3 on
+					probe DB_LTE LTE_PCIE
+				end
+			end
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
+				register "add_acpi_dma_property" = "true"
+				use rp6_rtd3 as rtd3dev
+				device generic 0 on
+					probe DB_LTE LTE_PCIE
+				end
+			end
+			probe DB_LTE LTE_PCIE
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98357_ALC5682I_I2S
+					probe AUDIO MAX98360_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/nau8825
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+				register "jkdet_enable" = "1"
+				register "jkdet_pull_enable" = "0"
+				register "jkdet_polarity" = "1"		# ActiveLow
+				register "vref_impedance" = "2"		# 125kOhm
+				register "micbias_voltage" = "6"	# 2.754
+				register "sar_threshold_num" = "4"
+				register "sar_threshold[0]" = "0x0c"
+				register "sar_threshold[1]" = "0x1c"
+				register "sar_threshold[2]" = "0x38"
+				register "sar_threshold[3]" = "0x60"
+				register "sar_hysteresis" = "1"
+				register "sar_voltage" = "0"		# VDDA
+				register "sar_compare_time" = "0"	# 500ns
+				register "sar_sampling_time" = "0"	# 2us
+				register "short_key_debounce" = "2"	# 100ms
+				register "jack_insert_debounce" = "7"	# 512ms
+				register "jack_eject_debounce" = "7"	# 512ms
+				device i2c 1a on
+					probe AUDIO ALC1019_NAU88L25B_I2S
+				end
+			end
+			chip drivers/generic/alc1015
+				register "hid" = ""RTL1019""
+				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				device generic 1 on
+					probe AUDIO ALC1019_NAU88L25B_I2S
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "360 * MHz" # 360 MHz
+				register "link_freq[1]" = "180 * MHz" # 180 MHz
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 10 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "2"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW9768 VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9768""
+
+				device i2c 0C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""AT24 EEPROM""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
+				register "nvm_compat" = ""atmel,24c1024""
+
+				register "nvm_size" = "0x2800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x10"
+
+				device i2c 58 on end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end #I2C1
+		device ref i2c2 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR1 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x00"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x07"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x07"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0f"
+				register "reg_prox_ctrl0" = "0x12"
+				register "reg_prox_ctrl1" = "0x12"
+				register "reg_prox_ctrl2" = "0x90"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x12"
+				register "reg_prox_ctrl6" = "0x3c"
+				register "reg_prox_ctrl7" = "0x58"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x5c"
+				register "reg_adv_ctrl11" = "0x52"
+				register "reg_adv_ctrl12" = "0xb5"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x38"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0xf0"
+				register "reg_adv_ctrl20" = "0xf0"
+				device i2c 28 on end
+			end
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR2 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "2"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x00"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x07"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x07"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0f"
+				register "reg_prox_ctrl0" = "0x12"
+				register "reg_prox_ctrl1" = "0x12"
+				register "reg_prox_ctrl2" = "0x90"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x12"
+				register "reg_prox_ctrl6" = "0x3c"
+				register "reg_prox_ctrl7" = "0x58"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x5c"
+				register "reg_adv_ctrl11" = "0x52"
+				register "reg_adv_ctrl12" = "0xb5"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x38"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0xf0"
+				register "reg_adv_ctrl20" = "0xf0"
+				device i2c 2C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3478""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""imx 208 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "384 * MHz" # 384 MHz
+				register "link_freq[1]" = "96 * MHz" # 96 MHz
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C3"  #PP3300_FCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset
+				register "gpio_panel.gpio[3].gpio_num" = "GPP_H21" #CLK_EN
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(3, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(3, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 10 on
+					probe UFC UFC_MIPI_IMX208
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""ACPI_DT_NAMESPACE_HID""
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""GT24C16S""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
+				register "nvm_compat" = ""atmel,24c1024""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				device i2c 50 on
+					probe UFC UFC_MIPI_IMX208
+				end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""GOOG0020""
+				register "desc" = ""Chrome OS HPS""
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"  # EN_HPS_PWR
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)"  # HPS_INT_ODL
+				# HPS uses I2C addresses 0x30 and 0x51.
+				# The address we provide here is not significant because
+				# neither coreboot nor Linux have a driver for HPS,
+				# it's only used from userspace.
+				device i2c 30 on
+					probe HPS HPS_PRESENT
+				end
+			end
+		end #I2C2
+		device ref i2c3 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9050""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.stop_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x5d on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SIS9815""
+				register "generic.desc" = ""SIS Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.stop_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "100"
+				register "generic.enable_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "7"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x00"
+				device i2c 5c on end
+			end
+		end #I2C3
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end #I2C5
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98357A""
+				register "sdmode_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO MAX98357_ALC5682I_I2S
+				end
+			end
+
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO MAX98360_ALC5682I_I2S
+				end
+			end
+
+			chip drivers/intel/soundwire
+				device generic 0 on
+					probe AUDIO MAX98373_ALC5682_SNDW
+					chip drivers/soundwire/alc5682
+						# SoundWire Link 0 ID 1
+						register "desc" = ""Headset Codec""
+						device generic 0.1 on end
+					end
+					chip drivers/soundwire/max98373
+						# SoundWire Link 2 ID 3
+						register "desc" = ""Left Speaker Amp""
+						device generic 2.3 on end
+					end
+					chip drivers/soundwire/max98373
+						# SoundWire Link 2 ID 7
+						register "desc" = ""Right Speaker Amp""
+						device generic 2.7 on end
+					end
+				end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				use conn2 as mux_conn[2]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 2 alias conn2 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on
+							probe UFC UFC_USB
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/skolas4es/ramstage.c b/src/mainboard/google/brya/variants/skolas4es/ramstage.c
new file mode 100644
index 0000000000..970c628f50
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/ramstage.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	/* All values are for baseline config as per bug:191906315 comment #10 */
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}
diff --git a/src/mainboard/google/brya/variants/skolas4es/variant.c b/src/mainboard/google/brya/variants/skolas4es/variant.c
new file mode 100644
index 0000000000..e9ae51ea0f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/skolas4es/variant.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							MAX98373_ALC5682_SNDW));
+}