diff options
| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-05-25 20:20:34 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 13:14:16 +0000 |
| commit | 463f28852239f58fadf842eff21a9d58cb167774 (patch) | |
| tree | b0d9293d850dcfb1456fbf0b84b4e9a5e85bfc04 /src/mainboard/google/brya | |
| parent | c675d410e706d2e0a47d122a96d19f0b2253d10e (diff) | |
mb/google/brask/variants/moli: enable USB retimer
Enable USB retimer in moli overridetree.
BUG=b:233869074
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/overridetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 4433c5b7c9..6aa0464b49 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -34,6 +34,13 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end # USB4 Port device ref pcie4_0 on # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ |