mb/google/brya/var/omnigul: Add ADL and RPL dptf settings

Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul

BUG=b:273415170
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

3 files changed, 128 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/variants/omnigul/Makefile.inc b/src/mainboard/google/brya/variants/omnigul/Makefile.inc
index 8843e0d9e2..810ceb25bc 100644
--- a/src/mainboard/google/brya/variants/omnigul/Makefile.inc
+++ b/src/mainboard/google/brya/variants/omnigul/Makefile.inc
@@ -5,6 +5,8 @@ ramstage-y += gpio.c
 
 ramstage-y += variant.c
 
+ramstage-y += ramstage.c
+
 romstage-y += gpio.c
 
 romstage-y += memory.c
diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
index 00e4eec491..2af7db4288 100644
--- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb
+++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
@@ -82,7 +82,115 @@ chip soc/intel/alderlake
 	# Enable the Cnvi BT Audio Offload
 	register "cnvi_bt_audio_offload" = "1"
 
+	register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 123,
+	}"
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 114,
+	}"
+
+	register "tcc_offset" = "8"
+
 	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(95, 100),
+								TEMP_PCT(52, 46),
+								TEMP_PCT(46, 40),
+								TEMP_PCT(41, 35),
+								TEMP_PCT(40, 28),
+								TEMP_PCT(34, 26),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_1,
+						.thresholds = {
+								TEMP_PCT(60, 100),
+								TEMP_PCT(55, 46),
+								TEMP_PCT(49, 40),
+								TEMP_PCT(45, 35),
+								TEMP_PCT(40, 28),
+								TEMP_PCT(35, 26),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 70, 5000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 70, 5000),
+					[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 70, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               100, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 15000,
+						.max_power = 25000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 500,
+					},
+					.pl2 = {
+						.min_power = 55000,
+						.max_power = 55000,
+						.time_window_min = 32 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 500,
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
diff --git a/src/mainboard/google/brya/variants/omnigul/ramstage.c b/src/mainboard/google/brya/variants/omnigul/ramstage.c
new file mode 100644
index 0000000000..a2088752a0
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/ramstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 25000, 55000, 55000, 123000 },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 25000, 55000, 55000, 123000 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 25000, 55000, 55000, 114000 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 25000, 55000, 55000, 114000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}