diff options
| author | Tarun Tuli <taruntuli@google.com> | 2023-04-20 18:01:33 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-22 16:25:50 +0000 |
| commit | 1c25808f0bd5509eb438063c26b58134d8f54ba9 (patch) | |
| tree | 0b67fbefcbc56a7291d9b2c9e7e0fbed6b63c556 /src/mainboard/google/brya | |
| parent | dbf132cc1ea81bb6f5ce95d3105986cacc29eafe (diff) | |
mb/google/brya/variants/hades: Swap LAN and SD Card PCIE Ports
To aid in layout, the PCI ports for LAN and SD card were swapped.
SD Card is now on RP3 (clksrc 4)
LAN is now on RP8 (clksrc 3)
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/hades/overridetree.cb | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index 9c9171c458..1412a1ff6a 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -211,10 +211,27 @@ chip soc/intel/alderlake end end device ref pcie_rp3 on - # Enable PCIE 3 using clk 4 + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + # Enable SD Card PCIE 3 using clk 4 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 SD card + device ref pcie_rp4 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 on + # Enable PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip drivers/net @@ -225,23 +242,6 @@ chip soc/intel/alderlake device pci 00.0 on end end end #RTL8111H Ethernet NIC - device ref pcie_rp4 off end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 on - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" - register "srcclk_pin" = "3" - device generic 0 on end - end - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 register "pch_pcie_rp[PCH_RP(9)]" = "{ |