diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2022-02-08 17:24:18 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-02-09 17:56:29 +0000 |
| commit | 110e5ced756af7e3338e488fa277364dc4f5d846 (patch) | |
| tree | e7696e001622643b4e13e870e66a88bc66c9ced3 /src/mainboard/google/brya | |
| parent | ababf01e0ef59d265607355ea551c8869636dfc2 (diff) | |
mb/google/brya/var/volmar: enable RTD3 for PCIe-eMMC bridge
1. Enable RTD3 driver for PCIe-eMMC bridge
2. Add fw_config entries for boot device.
BUG=b:211362308
TEST=Build and boot into eMMC storage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic9ef372fa963b040c5196aaf13f2ffde27c168d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/volmar/overridetree.cb | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index 80c1fd6261..00de8f5b5b 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -11,6 +11,14 @@ fw_config option AUDIO_UNKNOWN 0 option MAX98373_NAU88L25B_I2S 1 end + field BOOT_NVME_MASK 8 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_EMMC_MASK 9 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" @@ -181,6 +189,7 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref cnvi_wifi on chip drivers/wifi/generic @@ -283,12 +292,18 @@ chip soc/intel/alderlake end end device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "4" + device generic 0 alias emmc_rtd3 on end + end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 4 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end #PCIE3 BH799BB device ref pcie_rp6 off end # PCIE6 WWAN device ref pcie_rp8 off end # PCIE8 SD card |