diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2022-02-07 16:48:51 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-09 23:26:10 +0000 |
| commit | 0ce69258497360d003baeb083937d11a7519002d (patch) | |
| tree | 6b6df9fe5a0513243c5e026abc352284ee3f5c67 /src/mainboard/google/brya | |
| parent | a2322df64ee88cb13133af241657faf2de44ee92 (diff) | |
mb/google/var/kano: Add gpios to lock
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
kano boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/gpio.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 57975f7040..8ef3c39a0f 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -27,7 +27,7 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_A22, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */ @@ -37,11 +37,11 @@ static const struct pad_config override_gpio_table[] = { /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC(GPP_D8, NONE), /* D16 : ISH_UART0_CTS# ==> PEN_PWR_EN */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), /* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */ - PAD_CFG_GPI_SCI(GPP_D17, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> NC */ - PAD_NC(GPP_D18, NONE), + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -50,9 +50,9 @@ static const struct pad_config override_gpio_table[] = { /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ @@ -72,9 +72,9 @@ static const struct pad_config override_gpio_table[] = { /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H12 : I2C7_SDA ==> NC */ - PAD_NC(GPP_H12, NONE), + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> NC */ - PAD_NC(GPP_H13, NONE), + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H20 : IMGCLKOUT1 ==> NC */ |