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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-05-31 20:41:31 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-21 05:40:05 +0000 |
| commit | 0185489c0d4e0b0823047a5a617bed3b6742e04c (patch) | |
| tree | 8bad0980c573b05735eea41e8a3c3142f517df69 /src/mainboard/google/brya | |
| parent | f8b237b28df43c6cb58d1ca8eb61bc483a327f8c (diff) | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01
The headers added are generated as per FSP v2207_01.
Previous FSP version was v2162_00.
Changes Include:
- Add IbeccProtectedRangeEnable, IbeccProtectedRangeBase and
IbeccProtectedRangeMask in FspmUpd.h
- Add UsbTcPortEn in FspsUpd.h
- Adjust Reserved UPD Offset in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:189731004
BRANCH=None
TEST=Build and boot brya
Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd
Cq-Depend: chrome-internal:3876956, chrome-internal:3909162,
chrome-internal:3909163
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55094
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
0 files changed, 0 insertions, 0 deletions