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authorFrank Chu <Frank_Chu@pegatron.corp-partner.google.com>2022-12-07 12:43:00 +0800
committerMartin L Roth <gaumless@gmail.com>2022-12-10 17:55:35 +0000
commit0029840db9d340cffeba336057bf3e6257f046cb (patch)
treef17f032fd822028ddcc33eb0bbc59ee135cd1aed /src/mainboard/google/brya
parent6e23da2983f83c803cf4abfee542d7f90e8e9eb5 (diff)
mb/google/brya/var/marasov: Enable PCIe port 5 for WLAN
Enable PCIe port 5 for WLAN device BUG=b:261514079 BRANCH=firmware-brya-14505.B TEST=Build and boot on marasov. Ensure that the WLAN module is enumerated in the output of lspci. localhost ~ # lspci 01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I007501bb00e2b7b83de1292f3066874d07646cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70442 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
-rw-r--r--src/mainboard/google/brya/variants/marasov/overridetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index 09af8fa1ac..b7faf0f8a1 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -163,6 +163,24 @@ chip soc/intel/alderlake
device i2c 15 on end
end
end #I2C5
+ device ref pcie_rp5 on
+ # Enable wlan PCIe 5 using clk 2
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_DW1_03"
+ device pci 00.0 on end
+ end
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+ register "srcclk_pin" = "2"
+ device generic 0 on end
+ end
+ end
device ref pcie_rp11 on
# Enable NVMe SSD PCIe 11-12 using clk 1
register "pch_pcie_rp[PCH_RP(11)]" = "{