mb/google/brya/var/osiris: Enable CsPiStartHighinEct for Hynix memory

According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.

BUG=b:284192689
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.

Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

2 files changed, 146 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/variants/osiris/Makefile.inc b/src/mainboard/google/brya/variants/osiris/Makefile.inc
index 9ea19ded56..75adb9982c 100644
--- a/src/mainboard/google/brya/variants/osiris/Makefile.inc
+++ b/src/mainboard/google/brya/variants/osiris/Makefile.inc
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/osiris/memory.c b/src/mainboard/google/brya/variants/osiris/memory.c
new file mode 100644
index 0000000000..564289875f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/osiris/memory.c
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <memory_info.h>
+#include <string.h>
+
+static const struct mb_cfg osiris_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
+			.dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
+		},
+		.ddr1 = {
+			.dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
+			.dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
+			.dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
+			.dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
+		},
+		.ddr4 = {
+			.dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
+			.dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
+		},
+		.ddr5 = {
+			.dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
+			.dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
+		},
+		.ddr6 = {
+			.dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
+			.dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
+			.dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+static const struct mb_cfg hynix_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
+			.dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
+		},
+		.ddr1 = {
+			.dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
+			.dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
+			.dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
+			.dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
+		},
+		.ddr4 = {
+			.dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
+			.dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
+		},
+		.ddr5 = {
+			.dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
+			.dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
+		},
+		.ddr6 = {
+			.dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
+			.dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
+			.dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+
+	.cs_pi_start_high_in_ect = 1,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	const char *part_num = mainboard_get_dram_part_num();
+	const char *hynix_mem1 = "H54G46CYRBX267";
+	const char *hynix_mem2 = "H54G56CYRBX247";
+
+	if (!strcmp(part_num, hynix_mem1) || !strcmp(part_num, hynix_mem2)) {
+		printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix memory\n");
+		return &hynix_memcfg;
+	} else {
+		return &osiris_memcfg;
+	}
+}