diff options
| author | Weimin Wu <wuweimin@huaqin.corp-partner.google.com> | 2023-12-06 23:06:15 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-08 12:55:58 +0000 |
| commit | c6fd32d131927930738bbdf2b3562863135bdda8 (patch) | |
| tree | 2b48f51792f4b5bc19c78c915563b66c7484d340 /src/mainboard/google/brya | |
| parent | 2eeec43379583cca946296fc4e88e57cad00ef75 (diff) | |
mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthcharge
Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged, keep mainboard C port to conn0.
BUG=b:312998945
TEST=can boot from external Type-c USB disk
Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/overridetree.cb | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index b4b16599be..0983257867 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -56,7 +56,7 @@ chip soc/intel/alderlake # motherboard to USBC connector register "tcss_aux_ori" = "4" - register "typec_aux_bias_pads[1]" = "{ + register "typec_aux_bias_pads[0]" = "{ .pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23 }" @@ -366,8 +366,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[1] - use conn1 as mux_conn[0] + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -375,13 +375,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - use usb2_port2 as usb2_port - use tcss_usb3_port1 as usb3_port + use usb2_port1 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port - use tcss_usb3_port2 as usb3_port + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 1 alias conn1 on end end end @@ -391,18 +391,18 @@ chip soc/intel/alderlake chip drivers/usb/acpi device ref tcss_root_hub on chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (DB)"" + register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port1 on end + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port2 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port2 on end + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end end end end |