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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2021-11-10 12:26:22 +0800
committerPaul Fagerburg <pfagerburg@chromium.org>2021-11-11 22:45:42 +0000
commitbfc4d8ef1c27d193e8428735e4114f714457b1df (patch)
tree8125cbb54940ad8183d4df6d56118751e101f000 /src/mainboard/google/brya
parent4f8aea05944129e9fee7692c413fabe1ab287d0a (diff)
mb/google/brya/var/kano: Configure USB2 and USB3 port
Disable unused USB2 and USB3 port BUG=b:192370253 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
-rw-r--r--src/mainboard/google/brya/variants/kano/overridetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index f2b04db46d..8aca8b4584 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -18,6 +18,12 @@ chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_D"
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable M.2 Bluetooth
+
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
+
# FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{