diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2022-02-07 16:12:14 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-09 23:25:56 +0000 |
| commit | a2322df64ee88cb13133af241657faf2de44ee92 (patch) | |
| tree | 2c44d652484edfcdc8e31ea2e8f789602919d614 /src/mainboard/google/brya | |
| parent | e6460a47777545919c80274322885e6a5d1e886a (diff) | |
mb/google/var/gimble4es: Add gpios to lock
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
gimble boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If71ceb07a9894a0571a9983d008058598693986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble4es/gpio.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c index 5606733bd8..a4ed7fb60b 100644 --- a/src/mainboard/google/brya/variants/gimble4es/gpio.c +++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c @@ -27,11 +27,11 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_A22, NONE), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -43,17 +43,17 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_C4, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D9 : ISH_SPI_CS# ==> NC */ - PAD_NC(GPP_D9, NONE), + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -64,11 +64,11 @@ static const struct pad_config override_gpio_table[] = { /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> NC */ PAD_NC(GPP_E18, NONE), /* E20 : DDP2_CTRLCLK ==> NC */ |