diff options
| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2022-05-26 16:36:52 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-06-01 01:41:22 +0000 |
| commit | 850925ff000d5c43e4d8cd76af35a8c7f39f6efe (patch) | |
| tree | edc771fa29e9515dfc161d7c16fddba53516186f /src/mainboard/google/brya | |
| parent | fef198f3020b2055c010d2032c940cf98de452e2 (diff) | |
mb/google/brya/var/kinox: Add delay time for BH799BB rtd3
This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:232327947
TEST=Build and suspend_stress_test -c 2500 pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/kinox/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 2646b630fa..7aa253635e 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -206,6 +206,8 @@ chip soc/intel/alderlake register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" register "srcclk_pin" = "1" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end end # BH799BBLN |