diff options
| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-02-25 20:24:01 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-10 15:13:09 +0000 |
| commit | 1c14957254ced5eb8cfb4f20230422d951a9ffac (patch) | |
| tree | 195b03329f66f44bbbbdd31d65ea18f9712f6997 /src/mainboard/google/brya | |
| parent | c397f004b7abdaf5a6950299b2d24fa4f72a435f (diff) | |
mb/google/brask/variants/moli: Reduce PSysMax to 11 A
Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W
BUG=b:215258941
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/ramstage.c | 38 |
2 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc index 6c29346470..aa151d64f5 100644 --- a/src/mainboard/google/brya/variants/moli/Makefile.inc +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c new file mode 100644 index 0000000000..5690156c50 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/ramstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 135 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 135 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 135 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 230 }, +}; + +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 11000, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} |