diff options
| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2022-04-07 16:10:31 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-20 19:49:32 +0000 |
| commit | 161e731d7e6b3c23268c2f3916f2e0613741bc87 (patch) | |
| tree | ae37effeae72ee879cc9879ec6f676e178be43dc /src/mainboard/google/brya | |
| parent | 9aa7a25c2d0eec48f8adcfeb73e14ac006cad8a8 (diff) | |
mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The
default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.
BUG=b:228929196
TEST=emerge-brya coreboot and pass RF test as before
Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index fd5f27a6ff..a2fe72d239 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -71,6 +71,9 @@ chip soc/intel/alderlake register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" register "sagv" = "SaGv_Enabled" + # FIVR RFI Spread Spectrum 6% + register "fivr_spread_spectrum" = "FIVR_SS_6" + # I2C Port Config register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |