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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2021-11-17 15:58:25 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-11-18 23:32:43 +0000
commiteae7bf2327f7f1fab7c0177e5ee2116b624a92a9 (patch)
tree28c9623652115fb08b2af7f182a3bd716a86b8d2 /src/mainboard/google/brya/variants
parent88295c35cc06bc0650111d2f92e0b7235b7164b0 (diff)
mb/google/brya/var/felwinter: Correct USB3 TCSS setting
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/felwinter/overridetree.cb12
-rw-r--r--src/mainboard/google/brya/variants/felwinter/variant.c1
2 files changed, 10 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 5b90b9acb0..b1980f6095 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -38,6 +38,12 @@ chip soc/intel/alderlake
device domain 0 on
device ref dtt on end
device ref tbt_pcie_rp0 off end
+ device ref tbt_pcie_rp1 on
+ probe DB_USB USB4_KB8001
+ end
+ device ref tbt_pcie_rp2 on
+ probe DB_USB USB4_KB8001
+ end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
@@ -45,6 +51,7 @@ chip soc/intel/alderlake
end
end
device ref tcss_dma0 on
+ probe DB_USB USB4_KB8001
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port2 as dfp[0].typec_port
@@ -52,12 +59,11 @@ chip soc/intel/alderlake
end
end
device ref tcss_dma1 on
+ probe DB_USB USB4_KB8001
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port3 as dfp[0].typec_port
- device generic 0 on
- probe DB_USB USB4_KB8001
- end
+ device generic 0 on end
end
end
device ref pcie_rp6 off end
diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c
index 9234019952..ee39ef080e 100644
--- a/src/mainboard/google/brya/variants/felwinter/variant.c
+++ b/src/mainboard/google/brya/variants/felwinter/variant.c
@@ -9,5 +9,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) {
config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19;
config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20;
+ config->TcssAuxOri = 0x10;
}
}