diff options
| author | YH Lin <yueherngl@google.com> | 2024-06-06 16:14:01 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-07 18:42:23 +0000 |
| commit | d401e10c573c259ae3143895d56758c03db0e595 (patch) | |
| tree | bfca9ae67e9d1fa1fabb00b78ea0aefbc91ee5b6 /src/mainboard/google/brya/variants | |
| parent | 49acc32cba994b0b663aca034e114abffd914a6f (diff) | |
mb/google/brya/var/xol: add support for wifi sar table
Add wifi sar table support for xol. Bit 31 in CBI/FW_CONFIG
is used to select different sar table (index 0 or 1) but only
0 is in used at the moment.
BUG=b:344274789
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: Id4dc74c4f2a807d2e531b419ecb7b590d4c32ac2
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/Makefile.mk | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/overridetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/variant.c | 11 |
3 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/xol/Makefile.mk b/src/mainboard/google/brya/variants/xol/Makefile.mk index c346b0abc9..d85ce1bfbe 100644 --- a/src/mainboard/google/brya/variants/xol/Makefile.mk +++ b/src/mainboard/google/brya/variants/xol/Makefile.mk @@ -4,3 +4,4 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index e1568f50b9..d73702c4bb 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -3,6 +3,10 @@ fw_config option STORAGE_UFS 0 option STORAGE_NVME 1 end + field WIFI_SAR_ID 31 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + end end chip soc/intel/alderlake diff --git a/src/mainboard/google/brya/variants/xol/variant.c b/src/mainboard/google/brya/variants/xol/variant.c new file mode 100644 index 0000000000..26ced214d4 --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/variant.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} |