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authorMark Hsieh <mark_hsieh@wistron.corp-partner.google.com>2021-11-09 21:45:08 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-11-11 14:33:12 +0000
commitb11de6fa0993086557d4c503dcb1af7e0ef98d74 (patch)
tree9c0f7adca4f649a582ae0737c48543ee35daea35 /src/mainboard/google/brya/variants
parentfb05b820ebdf06a47cc36e189d86aea02637fe1a (diff)
mb/google/brya/variants/gimble: Update audio setting for SmartAMP
Divide dsm_param_file_name into dsm_param_R and dsm_param_L BUG=b:205684021 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/gimble/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 8448594c1e..c015009c00 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -135,7 +135,7 @@ chip soc/intel/alderlake
register "name" = ""MXW0""
register "r0_calib_key" = ""dsm_calib_r0_0""
register "temperature_calib_key" = ""dsm_calib_temp_0""
- register "dsm_param_file_name" = ""dsm_param""
+ register "dsm_param_file_name" = ""dsm_param_R""
register "vmon_slot_no" = "0"
register "imon_slot_no" = "1"
device i2c 0x38 on
@@ -147,7 +147,7 @@ chip soc/intel/alderlake
register "name" = ""MXW1""
register "r0_calib_key" = ""dsm_calib_r0_1""
register "temperature_calib_key" = ""dsm_calib_temp_1""
- register "dsm_param_file_name" = ""dsm_param""
+ register "dsm_param_file_name" = ""dsm_param_L""
register "vmon_slot_no" = "1"
register "imon_slot_no" = "0"
device i2c 0x3c on