diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2021-03-08 15:22:00 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:25:14 +0000 |
| commit | 9b725cf31194d772b62d50f3653ad8772f31d0b6 (patch) | |
| tree | 4fb43d0dc4efaed9d63945569d4d354338def333 /src/mainboard/google/brya/variants | |
| parent | b1a128fc88803fa902ab7e78f41b749b3bb13f05 (diff) | |
mb/google/brya: Remove BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 8717e70a11..33be8623f7 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -24,6 +24,9 @@ chip soc/intel/alderlake register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + # Enable CNVi BT + register "CnviBtCore" = "true" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 @@ -103,7 +106,6 @@ chip soc/intel/alderlake device ref tcss_xhci on end device ref tcss_dma0 on end device ref tcss_dma1 on end - device ref cnvi_bt on end device ref xhci on end device ref shared_sram on end device ref cnvi_wifi on |