diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-16 13:52:52 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 14:52:05 +0000 |
| commit | 5a0432182fc0874d9b11305363000c68671a2f80 (patch) | |
| tree | a302d5040a3c813d3e743d70eda31365bcf9ee32 /src/mainboard/google/brya/variants | |
| parent | 895691a78377e7ac058b0734794ecbdb3a4ee689 (diff) | |
mb/google/brya/var/{anahera, anahera4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/overridetree.cb | 16 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera4es/overridetree.cb | 16 |
2 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index d2b4ea14da..da5b78baa5 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -319,7 +319,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + .group = ACPI_PLD_GROUP(2, 1)}" device ref tcss_usb3_port3 on end end end @@ -349,11 +349,11 @@ chip soc/intel/alderlake .panel = PLD_PANEL_LEFT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 2)}" + .group = ACPI_PLD_GROUP(3, 2)}" device ref usb2_port2 on end - end + end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "{ @@ -361,7 +361,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + .group = ACPI_PLD_GROUP(2, 1)}" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -383,7 +383,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -402,7 +402,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb3_port1 on end end chip drivers/usb/acpi @@ -414,7 +414,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_LEFT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 2)}" + .group = ACPI_PLD_GROUP(3, 2)}" device ref usb3_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index e383f17ced..6745779e8f 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -311,7 +311,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + .group = ACPI_PLD_GROUP(2, 1)}" device ref tcss_usb3_port3 on end end end @@ -341,11 +341,11 @@ chip soc/intel/alderlake .panel = PLD_PANEL_LEFT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 2)}" + .group = ACPI_PLD_GROUP(3, 2)}" device ref usb2_port2 on end - end + end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "{ @@ -353,7 +353,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + .group = ACPI_PLD_GROUP(2, 1)}" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -375,7 +375,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -394,7 +394,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_RIGHT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb3_port1 on end end chip drivers/usb/acpi @@ -406,7 +406,7 @@ chip soc/intel/alderlake .panel = PLD_PANEL_LEFT, .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 2)}" + .group = ACPI_PLD_GROUP(3, 2)}" device ref usb3_port3 on end end chip drivers/usb/acpi |